Electronic Design

Extremely Parallel Processor Sets New Benchmark

At July's Platform Conference in San Jose, fabless IP firm PACT Corp. of Munich, Germany, revealed plans to make the first derivative of its eXtreme processor platform (XPP) available for licensing. Comprising an array of 128 processing elements on-chip, the XPU128 parallel reconfigurable 32-bit engine performs over 50 billion operations per second (BOPS).

PACT cofounder and chief technology officer Martin Vorbach says the XPU128 consumes only about a tenth of the power of leading DSP designs at a 100-MHz clock. Also, the XPU128 will be implemented in both 0.18-µm and 0.15-µm design rules. Leading CPU and DSP suppliers are negotiating with PACT Corp. for licenses, but further details were unavailable.

The company hopes the XPU128 will be used in conjunction with a DSP core in SoC solutions for emerging 3G and 4G wireless basestations, as well as other compute-intensive high-bandwidth applications like media streams, data mining, simulation, and CAD. PACT is making this IP core available as an algorithmic coprocessor for leading CPU and DSP cores used in SoC chips.

"PACT's reconfigurable array of processing elements is extremely versatile and can be configured on-the-fly to perform in several classic ways, which include single-threaded pipeline processing, multithreading, multitasking, and even multiprocessor DSP operations," says Will Strauss, president of market research firm Forward Concepts, Tempe, Ariz. Plus, the basic parallel structure lends itself to high-performance matrix math operations, which are key for DSP operations that will be needed in 3G and 4G cellular basestations for multi-user detection and smart antennas.

The 50-BOPS XPU128 was first disclosed at last year's Microprocessor Forum (see the figure). The proof of concept was demonstrated there in 0.25-µm CMOS. According to PACT, XPP is a new class of processing engine that can do a lot more than conventional DSPs. It has been crafted to encompass the best of both microprocessor and DSP capabilities with massively parallel processing on the same chip.

Also, it's designed to offer modularity and scalability. This dynamically reconfigurable DSP engine can handle parallel processing tasks with unprecedented performance and bandwidth. It can map any form of algorithm into its multiple arithmetic logic units (ALUs), creating a virtual ASIC that can be reconfigured on-the-fly, erased, and rebuilt with zero latency. PACT believes the XPP takes DSPs to the next level in performance.

Since the XPP architecture is both modular and scalable, PACT's roadmap says future devices with over 400 BOPS can be expected in 2002. Over a trillion operations per second can be achieved within this decade by scaling both clock frequencies and the number of processor array elements (PAEs). Utilizing advanced processes, PACT designers hope to integrate over 1000 PAEs on a single die before the end of this decade.

PACT also has readied an integrated XPP development suite, which includes a compiler and mapper for the native mapping language (NML), a simulator, and an interactive visualization and debugging tool. For details, visit www.pactcorp.com.

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