Electronic Design

Processor Vendors Target Small Basestations

 

 

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To support a shift to smaller cellular basestations, chip makers are seeking ways to reduce system cost. Integrating the CPU and DSP on the same chip is essential to meeting these lower cost targets. Yet this integration sets up a collision between Freescale, the leading supplier of processors for basestations, and Texas Instruments, the leading vendor of DSP chips.

Smaller Basestations Needed                                                            

In a traditional cellular network, a single (macro) basestation covers a cell that can be a mile or more across, limited mainly by the range of the cell phone’s radio. This arrangement minimizes the number of expensive basestations that a carrier must deploy, but it creates some problems.

First, the number of available channels (radio frequencies) limits the number of users (devices) that can be active within a single cell. Another problem is that the newer 3G and 4G protocols deliver high data rates only for short ranges. As users move farther from the basestation’s antenna, reception degrades. Thus, in a large cell, only users in a small portion of that cell can achieve the maximum data rates.

The solution to both problems is to reduce cell size by deploying more basestations. In a small cell, users are on average much closer to the antenna, enabling higher data rates. Furthermore, splitting a large cell into several smaller cells reduces the number of users in each cell and therefore the number of users per channel. Thus, each user can access more of the channel bandwidth.

To support this trend, basestation makers are developing smaller, less expensive models. The carrier typically deploys microcells and picocells, whereas femtocells are deployed in either businesses (enterprise) or residences. Residential femtocells typically support four to eight users, whereas enterprise femtocells support 16 to 64 users. Microcells and picocells typically support 128 to 256 users.

Combining CPU And DSP

TI’s new Keystone chips target enterprise femtocells and picocells. These processors combine a 1.2-GHz Cortex-A8 (ARM) CPU with either two or four of TI’s C66x DSP cores, also running at 1.2 GHz. The C66x is the company’s newest DSP design, capable of high performance on either fixed- or floating-point algorithms. The chips support 3G and 4G protocols at up to 300 Mbits/s and can handle 128 users. They are due to sample in the third quarter of 2011.

In this design, the CPU runs the Layer 3 (IP) code, whereas the DSP runs the Layer 2 and Layer 1 firmware for baseband processing. This processing is typically run on fixed-point DSPs to reduce die area and cost. Although the C66x performs very well on fixed-point code, TI offers the floating-point mode for greater precision, which is useful in multi-antenna (MIMO) protocols and some scheduling algorithms.

KeyStone provides a variety of hardware accelerators to help the CPU and DSP cores achieve high throughput. The chip offloads common Layer 1 tasks from the DSPs, including fast Fourier transforms (FFTs), Viterbi decoding, turbo encoding and decoding, and WCDMA transmit and receive.

Freescale calls its CPU-DSP products Qonverge. The initial Qonverge products, also sampling in the third quarter of 2011, target residential and enterprise femtocells, although Freescale plans to develop high-end versions in the future. Like KeyStone, these products support a full range of cellular protocols including Long-Term Evolution (LTE).

Qonverge includes one or two of Freescale’s e500 PowerPC CPUs, which the company also sells into larger basestations. Supporting these CPUs are up to two of the company’s SC3850 StarCore DSPs. The CPUs and DSPs all operate at 1.2 GHz. Freescale adds a set of hardware accelerators called Maple that offload the DSPs, performing functions similar to those in KeyStone’s accelerators.

Keystone Versus Qonverge

KeyStone and Qonverge have many similarities. They include CPUs, DSPs, and a number of hardware accelerators. Both TI and Freescale provide firmware for popular 3G and 4G protocols. Freescale has the advantage of offering a CDMA stack, giving it a leg up with Verizon and other CDMA carriers that are moving to LTE. TI, however, offers a more complete system solution, including analog and RF components.

It is perhaps unsurprising that TI’s approach is more DSP-centric whereas Freescale’s design is more CPU-centric. The dual 1.2-GHz superscalar CPUs in Qonverge should easily outperform KeyStone’s single Cortex-A8 CPU. Freescale needs this performance because it uses the CPU for the Layer 2 scheduler, a task that TI performs in the DSP cores.

On the critical metric of cellular bandwidth, the combination of the wide single-instruction multiple-data (SIMD) units and the powerful offload engines helps KeyStone achieve twice the rated downlink speed of Qonverge in LTE mode. KeyStone also uses about twice the power of the Qonverge processor, however, indicating that the comparison depends more on the two companies’ chosen design point than their architectures.

TI chose to focus initially on mid-sized basestations, extending downward from traditional metro designs, whereas Freescale is starting with femtocells and working up. In femtocells, Freescale must compete with smaller companies such as Picochip and Percello (now part of Broadcom), but neither of these vendors supports LTE.

Many large basestation vendors have extensive software both for PowerPC and for TI’s DSPs, which until recently they purchased as separate chips. With the merging of the CPU and DSP on one chip, these system designers must now decide which of their two favorite vendors to dump. The fate of millions of basestations awaits their decisions.

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