The worldwide electronics and EDA industry may have something to cheer about in 2012-2013 and beyond, thanks to those inimitable software developers at social media companies such as Facebook, LinkedIn, and Twitter. Or, the industry can give a shout out to companies offering streaming video as Netflix and others offer ways to painlessly rent movies and video on the Web.
These companies have created a huge, insatiable demand for social media and video carried over the Internet. And while they may be providing loads of ways to keep us entertained, they’re overloading the network.
If this trend seems familiar, it is. The telecommunications infrastructure needed an overhaul between 1998 and 2000 as the Internet became an increasingly important form of communication. It was also a time of economic prosperity for the electronics and EDA industry.
More Bandwidth, Please
There’s no question that this phenomenon is driving bandwidth, as it did more than 11 years ago, which means the network infrastructure needs another overhaul in the form of more available bandwidth sooner rather than later. That’s good news for the electronics and EDA industry and foretells good fortune for both, if they take advantage of the opportunity.
Electronics companies will need to provide new and more complex networking chips, further pushing Moore’s law to its limit. In some cases, companies are already quadrupling the amount of complexity and processing power from one generation of their chip to the next in 12 months or less. Graphics processing chips continue to lead the pack with design sizes now in the hundreds of millions of ASIC-equivalent gates.
Mobile devices, heavily laden with functions, add another layer of complexity and challenge to chip design. The Apple iPhone, for example, has more than 500,000 apps and every downloaded app allows the phone do even more, pressuring other mobile phone providers to follow suit. We may see more offering 4G upgrades in the United States, upping the ante once more.
The days of broken promises, inadequate results, and user frustration are over for EDA. These new monster system-on-a-chip (SoC) designs with hundreds of gigabits of memory contain a mix of hardware and embedded software, presenting a tremendous opportunity for EDA. The industry needs to step up to the challenge.
Designers will need more powerful hardware and software tools across the design flow, from ESL and synthesis through place and route. Verification suppliers may be the most notable beneficiaries of bandwidth overload because these tools will be a critical component to an evolving strategic verification plan. They need to be practical and cost effective. They also need to provide quality of results quickly and accurately. After all, when used effectively, verification tools ultimately determine whether the chip works as intended.
Emulation To The Rescue
The range and type of SoC verification tools is well known, including formal verification, model checking, simulation, testbench generation, debug, and emulation. Finally, emulation is a popular verification method for large SoC designs with tens of millions of equivalent logic gates and the tool I know best. More and more, it’s considered a universal verification tool.
Emulation gives SoC designers a way to validate hardware and software on billion-gate devices by exercising billions of clock cycles before committing a chip to silicon. It is especially useful as software content and design complexity increase. Moreover, emulation can test a wide range of design styles. Some emulators are priced to be budget friendly.
Today’s SoC designs combine numerous interconnected blocks, including multicore processors, DSPs, and a mix of internal and third-party intellectual property (IP), all supported by large and complex memory blocks. By modeling a design into a hardware implementation, emulation provides the most accurate and closest realization to real silicon. It is the only a way to ensure that all of the blocks are verified accurately and in a reasonable timeframe, something of upmost importance to mobile device, network, and baseband suppliers.
Emulators have rigorous debugging capabilities and work at multiple orders of magnitude faster than the venerable logic simulator, still in limited use in the early stages of RTL design verification for functional and timing verification. Emulation is generally accepted as a solution to the runtime performance problems associated with simulation.
Foretelling A Bright Future
Perhaps the electronics and EDA industry needs to look beyond the networking possibilities of social media and instead welcome the new opportunities it presents. EDA is an industry full of bright innovators who know how to develop new tools and methodologies to tackle all the design challenges, but especially those related to verification. That gives us something to cheer about in 2012 and a reason to be optimistic. We may be on the cusp of economic prosperity once more.
Lauro Rizzatti is general manager of EVE-USA. He has more than 30 years of experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing, and engineering.