Gigabit Ethernet switches seem so last year. Yet Vitesse Semiconductor's SparX-G16 and SparX-G24 system-on-a-chip (SoC) solutions reduce the number of required passive components in switch designs while adding security, quality of service (QoS), and cost savings. Targets include small office/home-office (SOHO), small-medium business (SMB), and small-medium enterprise (SME) desktop switches as well as consumer wireless and DSL broadband routers.
The SparX-G16 (VSC7389) and SparXG24 (VSC7390) are 16- and 24-port Gigabit Ethernet layer 2 switches (see the figure). Their eight integral 10/100/ 1000-Mbit/s copper physical-layer (PHY) transceivers cut size, cost, and power consumption thanks to their integral CPU and line-termination components. The VSC7389 has eight SGMII ports, while the VSC7390 has 16 SGMII ports.
Additional features like packet filtering, fine granularity rate shaping, Internet Protocol multicast, and processorbased address learning arise from the on-chip V-core processor, Vitesse's souped-up 8051 variant. This processor reduces the per instruction clock cycles from 12 to four, compared to a traditional 8051 external processor.
Designers developing a 24-port design normally would require a sevenor eight-chip solution along with additional power and ground plane provisions. Now, designers can accomplish the same thing with the SparX-G24 and two Vitesse Octal PHYs.
The SparX devices include four queues per port with per-queue traffic shaping and policing, as well as IPv4 and IPv6 classification. They can carry consumer-quality Voice over Internet Protocol, too. Other key features include 802.1x authentication, layer 2 through 4 link aggregation, virtual local-area network (VLAN) support including Q-in-Q double VLAN tagging, and wirespeed media-access controller (MAC) address learning.
With the chips' Differentiated Service Code Point (DSCP) remarking, enterprise network managers and service providers can more accurately manage the priority of traffic based on service agreements with their customers. This functionality also decreases the threat of internal and external security breaches through packet filtering based on Source IP, ARP, and TCP/UDP filters. Flexible and configurable rate shaping for both ingress and egress enable enforcement of pre-negotiated bandwidth levels and up to 8k IP Multicast group entries for video distribution and other applications.
The chips consume less than 600 mW per port, which is 25% less than competitive multichip solutions. They also require only two supply voltages (3.3 and 1.2 V), dramatically lowering the overall system power-supply costs and reducing the number of pc-board layers to four. The on-chip termination resistors eliminate up to 300 external components for the 24G device.
The SparX devices are housed in a thermally enhanced PBGA package. Samples are available now. Volume pricing is $48 for the 16-port device and $64 for the 24-port device. An evaluation board also is available.
See the figure
Vitesse Semiconductor
www.vitesse.com
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