Electronic Design

  
Reprints     Printer-Friendly    Email this Article    RSS        Font Size     What's This?


[Basics Of Design]
Evaluate Platform ASIC Options To Match The Best Silicon To Your Application
Sponsored by: LSI LOGIC CORP.


Dave Bursky  |   ED Online ID #11303  |   November 7, 2005


When it comes to platform ASICs, designers have a wide range of options. Platform and structured ASIC solutions offer faster time-to-market and lower development costs than full cell-based ASIC designs. Additionally, they deliver more performance than high-density field-programmable gate arrays (FPGAs). Of course, you must evaluate your specific system needs and choose a platform ASIC accordingly.

Platform and structured ASICs have established themselves as attractive implementation options between custom-crafted cell-based ASICs and off-the-shelf FPGAs in terms of cost, performance, and complexity. These partially prefabricated chips can considerably reduce the mask costs and verification time and cost compared to a cell-based ASIC. They also can deliver higher performance and smaller chip sizes (and lower silicon costs) than high-density FPGAs.

Platform ASICs represent the higher end of this market segment. They tend to have more features than structured ASICs, offering more pre-integrated functionality in the form of multigigabit serializer/deserializers (SERDES), large amounts of embedded memory, phase-locked loops, and other functions.

Click here to download the PDF version of this entire article.


Reprints   Printer-Friendly  Email this Article  RSS    Font Size   What's This?


  • User Advisory Group To Guide Open Verification Methodology’s Evolution
  • DDR3 and DDR2 Memory IP Bolsters SoC Designs
  • PCB Tools Cross-Probe Between Layout And Schematic
  • Constraint-Driven Flow Targets PCB High-Density Interconnects
  • Cadence Abandons Its Bid To Buy Mentor Graphics
  • Model Extractor For CMOS Sports Improved RF/DC Parameters
  • 45-nm Via-Programmable ASICs Add High-Speed I/O Transceivers To Feature Mix
  • Get Ready For NIWeek
    1) SDR Transforms Amateur Radio
    (1132 views today)
    2) Low-Dropout (LDO) Linear Regulators
    (831 views today)
    3) DNA In Your Gadgets?
    (785 views today)
    4) Build A Smart Battery Charger Using A Single-Transistor Circuit
    (287 views today)
    5) A Summary Of The DDR Memory Controller Standard—Wait, There Isn’t One!
    (208 views today)
    ALL TOP 20



    POST YOUR COMMENTS HERE
    Name:

    Email:
    Your Comments:

    Enter the text from the image below


    Please refresh the page if you have trouble reading this text.

    Search Electronic Design
         
      
     
    Web Seminar
    Sponsored By:
    Title: Read Pacing: A Performance Enhancing Feature of PCI Express Gen 2 Switch Devices
    Speakers: 
    Date: 07/01/08
    Register: 

    Electronic Design Europe Electronic Design China EEPN Power Electronics Auto Electronics Microwaves & RF RF Design
    Schematics Find Power Products Military Electronics Featured Vendors EE Events Free Design Resources