Electronic Design

  
Reprints     Printer-Friendly    Email this Article    RSS        Font Size     What's This?


[Embedded Systems Conference]
Another 32-bit Core Goes On A Diet

William Wong  |   ED Online ID #15262  |   April 4, 2007


Putting out a new 32-bit microcontroller architecture is not something vendors do every day but last year Atmel introduced the AVR32 (see A New Player In The 32-Bit Procesor Field, ED Online 11939) line of microcontrollers. The first version targeted the high end of the spectrum. At this year’s ESC, Atmel is working to fill in the other end of the spectrum.

The AT32UC3A (Fig. 1) foregoes some of the features found in its older sibling. For example, the memory management unit has been replaced with a memory protection unit. This allows applications to be protected from one another but without the overhead needed for higher end operating systems like Linux and Windows CE. The protection unit handles 16 independent regions. Likewise, the big caches are gone. All this saves a sizable chunk of real estate and it actually makes the system more determinant. These features are more valuable in many embedded application areas. A split flash memory uses staggered access to double instruction delivery speed.

This 66MHz 80MIPS chip cuts the pipeline down to 3-stages (Fig. 2) and removes the Java support but it adds more bit field instructions and better interrupt handling. The chip is still targeted at applications that do some heavy number crunching as it keeps the DSP instruction set features that employ a single cycle fractional MAC (multiply/add/accumulate). For data transfers, the system employs DMA across the main bus matrix. It is designed to handle numerous bus masters simultaneously. The USB On-The-Go can be a master or slave device. Ethernet is the other major peripheral.

Nexus-compatible trace support augments the JTAG debug support. The 3.3V chip draws only 35ma at 66MHz. It has 64Kbytes of SRAM and 512Kbytes of flash. Pricing starts at $8.67.

Atmel had the older sibling on display as well with its $69 AVR32 Network Gateway kit (Fig. 3). It has an AT32AP7000 processor, 16-bit stereo audio DAC, 2048 by 2048 pixel TFT/STN LCD controller, high-speed USB 2.0 with on-chip PHY, and a pair of 10/100 Ethernet MACs. Interfaces include serial ports, I2S, AC97, TWI/I2C, SPI, PS/2 and several synchronous serial modules (SSC).

For more information, visit www.atmel.com.


Reprints   Printer-Friendly  Email this Article  RSS    Font Size   What's This?


  • C Tools Accelerate HDV Development On Xilinx FPGAs
  • A New Design Inflection Point
  • Forecasting Industry Growth For 2009 And Beyond
  • EDA Retools To Exploit Multicore Architectures
  • Design And Verification Move Up In Abstraction
  • EDA Retools To Exploit Multicore Architectures
  • A New Design Inflection Point
  • Design And Verification Move Up In Abstraction
    1) Transportation Guidelines For Lithium Batteries Get Updated
    (1283 views today)
    2) Build A Smart Battery Charger Using A Single-Transistor Circuit
    (290 views today)
    3) WHITE PAPER: Liquid-Level Monitoring Using a Pressure Sensor
    (235 views today)
    4) 1-A Switching Regulators Operate With 96% Efficiency To Replace Linear Regulators
    (149 views today)
    5) The Field Of Energy Harvesting Begins To Ripen
    (109 views today)
    ALL TOP 20



    POST YOUR COMMENTS HERE
    Name:

    Email:
    Your Comments:

    Enter the text from the image below


    Please refresh the page if you have trouble reading this text.

    Search Electronic Design
         
      
     
    Web Seminar
    Sponsored By:
    Title: Read Pacing: A Performance Enhancing Feature of PCI Express Gen 2 Switch Devices
    Speakers: 
    Date: 07/01/08
    Register: 

    Electronic Design Europe Electronic Design China EEPN Power Electronics Auto Electronics Microwaves & RF
    Mobile Dev & Design Schematics Find Power Products Military Electronics EE Events Related Resources