Seldom does a design team receive carte blanche—at whatever the cost—to meet performance or power specifications. But given the partitioning and segmentation of many IC design flows, it’s not uncommon for a particular team to optimize for one goal, say performance, without focusing on the implications it could have on the overall cost of the packaged chip.
Even the most conscientious and experienced designers know it isn’t easy to accurately predict the tradeoffs being made while keeping a design within functional specification boundaries. Will the architectural change adversely affect the overall power consumption? Will increasing performance cause the I/O count to increase so much that a ceramic package will be required?
Optimizing designs during implementation starts to feel like a game of whack-a-mole. Sometimes the next mole is so much larger and appears so much later in the design cycle that the whole design project risks getting, well, whacked.
Chip estimation systems have been used for years to accurately predict a chip’s die area, power, leakage, and cost before an IC design project gets the go-ahead (or before quoting a packaged die cost to an external customer). Yet a new methodology of using prediction systems alongside traditional EDA flows promises to deliver cost-awareness in a non-intrusive way.
Sort of like enhancing EDA with a fun and fast side-game of whack-a-mole. By telling the design team at any stage in the IC design process where the moles are, this methodology can be the best way to navigate around the moles without wasting scarce and costly implementation resources and time.
The Role of Chip Estimation Designers use chip estimation simply to avoid making mistakes. Mistakes are costly, and they’re becoming even more likely given the growing IP, technology, process node, and architectural options.
A broad spectrum of current chip-estimation methods ranges from simple mental calculations performed on napkins to spreadsheet analysis, sophisticated algorithms, and IP and technology data embedded in full-blown chip prediction systems. All of these methods are fast—measured in seconds and minutes—but their accuracy tends to vary.
The most advanced chip-estimation systems use macromodels of the data used by design implementation systems, combined with a user’s high-level design intent, to generate comprehensive chip plans in seconds and accurate to within 95% of silicon. The plans translate the users’ chip description or specification into a prediction of the reality they’ll face once their design is manufactured.
Acknowledging that achieving the desired functionality is seldom enough and falling within a certain cost range is what dictates the “go, no-go,” higher-end chip estimation systems also deliver comprehensive cost data.
Factors contributing to production chip cost should include volume-based package pricing. Silicon wafer pricing and defect density data allow systematic yield analysis, providing “good die” cost, test and assembly costs, and nonrecurring-engineering (NRE) cost data based on process-specific mask cost estimations.
The economic models that drive cost-calculation engines typically use Fabless Semiconductor Association reported statistical data. The more flexible systems allow users to tailor estimations based on their experience or foundry-partner data. Even return-on-investment (ROI) analysis is sometimes available, calculating the timeframe and volume over which NRE costs will be amortized as well as eventual design profitability.
With advanced systems, estimation results are formatted into charts, reports, and tables describing die area usage, chip bonding, dynamic and static power consumption, yield, and production chip cost. Given the speed of fast automated chip-estimation systems, it’s possible to generate and compare results for different scenarios and then tune the best plan.
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