Deep-submicron systems-on-a-chip (SoCs) require a power-grid voltage drop of much less than 10% of VDD. Decoupling capacitors, or decaps, help achieve this goal by minimizing switching noise. Determining the amount of decap required for an SoC involves many considerations, but the task needn’t be a chore. The approach described in this article allows you to allocate decap accurately and with minimal area overhead for deep-submicron (DSM) SoCs.
The method detailed here uses uniform placement (rather than structured relative placement) because the uniform approach has a smaller impact on congestion (both routing and placement) and can be part of a standard flow that doesn’t require custom structures. In fact, this method is now part of the design flow within the Synopsys Pilot Design Environment, implemented with Tcl scripts for floorplanning, incremental decap insertion, dynamic rail analysis, and debug.
Decap method overview
A key feature of the method is a phased approach with early estimation and a simple decap insertion implementation. Tests with a number of designs implemented by Synopsys Professional Services have shown that the best results are obtained if decaps are initially placed at the floorplanning stage. This approach enables you to make post-placement corrections easily if dynamic rail analysis indicates a need for additional decap cells.
Note that dynamic rail analysis is essential for designs at 90 nm or smaller. Static analysis provides a picture of voltage-drop problems, but it’s incomplete for DSM designs.
The analysis described in this article shows that you need to allocate between 7% and 10% of design area to decap cells. That may seem excessive, but at 90 nm and below, dynamic and static voltage drop is a significant problem.
Industry examples and rail analysis indicate that deep-submicron SoCs can suffer from performance issues and even functional failures without sufficient decap, so very high-performance designs can require that as much 20% of the placement area be dedicated to decoupling capacitors. The exact value for decap density varies according to each major block’s dynamic power density, since dynamic power density is proportional to operating frequency f.
For clarity, this article describes the decap method as it applies to an example SoC. The method applies equally well to a range of high-performance and handheld/mobile designs.
Estimating decap
For worst-case planning purposes, assume that decap comes entirely from dedicated Cox (gate-oxide capacitance) sources. Other intrinsic sources, such as inactive gate-junction capacitances and wire capacitance between adjacent VDD and VSS power grid nets, are ignored. A less pessimistic but reasonable assumption would be for 25% (in certain cases, as much as 50%) of the decoupling capacitance to come from intrinsic sources. In our case, we assumed 0% for an absolute worst-case estimate. At the block level, a slight refinement improves estimations: assume at least 25% of the decap comes from non-dedicated Cox sources.
For accurate analysis of decap requirements, you need good estimates of dynamic power consumption. A practical approach for getting these estimates at early design stages is to characterize the design for power based on published results for similar designs. The International Technology Roadmap for Semiconductors (ITRS) is helpful for this purpose (see the table). The table also highlights key technology parameters for copper interconnects.
From the ITRS table, choose a design whose characteristics are closest to your target design. By comparing the ITRS design characteristics with those of the target design, you can calculate a baseline decap requirement. To further refine your model, you can scale values for VDD and frequency to appropriate values.
For the purpose of illustrating recommended decap estimation and insertion techniques, we reference an example design throughout the following discussion. Our example design used the ARM1176 core running at a 350-MHz nominal clock frequency.
Using the method described here, we estimated power consumption of 104 mW at VDD = 1.0 V under typical operating conditions. With an estimated physical area of 4.989 mm2, this module clearly possesses a higher power density (and thus higher required decap density) compared to our example design’s video-output sub-module with its 267-MHz maximum clock frequency and area of 11.630 mm2.
For the example design’s core, the estimation method indicates a worst-case power density of approximately 4 W/cm2. Initial estimates indicate that the core requires a total of 25.680 nF of dedicated Cox decap.
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