David Maliniak
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ED Online ID #17338 |
September 25, 2007
EDA Alert
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EDA Alert e-Newsletter | September 25, 2007
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feature coverage |
Designing The Old-Fashioned Way By Michael Steinberger, Ph.D. Signal Integrity Software Inc. (SiSoft)
Some years ago, a prestigious investment firm ran television commercials in which a distinguished British actor proclaimed that "they make money the old-fashioned way. They earn it." In a similar vein, it'd be nice if it could be said of us electrical engineers that "we solve problems the old-fashioned way. We think." Unfortunately, we electrical engineers tend to be victims of our own success in that we're over-dependent on computers to do our analysis and measurements for us...
Come check out the Hotspots added to our Home Page, filled with all the latest EDA, analog, embedded, and power content from the ED Editors.
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Magma, UMC Team On 65-nm Physical Verification And DFM
Having recently completed joint qualification of Magma Design Automation's Quartz DRC, Quartz LVS, and Quartz DFM tools, Magma and UMC have rolled out a physical-verification and DFM flow for UMC's 65-nm process...
Takumi Technology Corp. is collaborating with Chartered Semiconductor Manufacturing Ltd. to validate Takumi's design-for-manufacturing (DFM) optimization software, Takumi Enhance, on Chartered's 65-nanometer (nm) process implementation of Common Platform technology...
Version 2.0b of AEi Systems' Power IC Model Library for the Cadence PSpice simulator is now available from EMA Design Automation. Version 2.0b has over 200 time-domain simulation models for power electronic designs. Several previously unavailable Texas Instruments (TI) models debut in version 2.0b, and future updates are anticipated to focus on many of TI's newest and most popular components...
RF/Microwave Design Suite Sports Accuracy And Speed
In the latest release of its Genesys RF/microwave design suite, Agilent Technologies has included new statistical and electromagnetic analyses that provide first-pass accuracy, resulting in shorter physical design cycles and faster time to market...
Guidelines for Mixed-Signal PHY IP Integration, Debug and Test
On October 10th a new Webcast presented by Electronic Design and sponsored by Synopsys will be held at 2pm ET. As high-speed serial interconnect IP cores such as PCI Express, SATA and XAUI are being integrated into deep-submicron 65- and 45-nm CMOS system-on-chips (SoC), a new array of design challenges are emerging not only for IP developers but also for SoC integrators. Take this opportunity to learn about a built-in self test feature, which enables at-speed analog testing on a pure digital tester.
Communications/Test Editor Louis E. Frenzel will look at the state of WiMAX in his October 25 Technology Report. How do you rate the technology's chances in the marketplace?
It will have a tough time competing against DSL, cable, 3G cell phones, and other technologies.
The technology is sound, but it still needs an infrastructure.
It won't be long before the U.S. catches up with the rest of the world in WiMAX adoption.
Power Electronics Technology Exhibition & Conference
More technical Content. More exhibits. More teardowns. More of what you need to know to find the right technologies, products and components to integrate into an ever-evolving array of complex applications. From Oct. 30 to Nov. 1, the Power Electronics Technology Exhibition & Conference, held in the Hilton Anatole hotel in Dallas, Texas, will give you the tools to optimize every element of the design process:
An educational program focuses on practical, day-to-day solutions;
A full contingent of suppliers demonstrating their latest innovations in the Exhibit Hall;
And a conference schedule that hits all of the high notes - digital and portable power, power design, conversion and management, magnetics, alternative energy, LED drivers and more.
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