Richard Gawel
|
ED Online ID #17339 |
October 11, 2007
Article Rating:
Not Rated
ED Update
If you are unable to view HTML, click here to view this message in your browser.
Electronic Design UPDATE e-Newsletter | October 10, 2007
True Circuits offers a complete family of PLLs and DLLs
Our clock generator, deskew, low-bandwidth, spread-spectrum, and high resolution PLLs and DDR DLLs are high-quality, low-jitter, silicon-proven hard macros. They are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in TSMC, UMC, CHRT, and Common Platform processes from 180 nm to 55 nm.
Electronic Design UPDATE edited by Richard Gawel, Managing Editor
.
.
Come check out the Hotspots added to our Home Page, filled with all the latest EDA, analog, embedded, and power content from the ED editors.
.
.
design solution |
Bringing Physical Predictability To Logic Design By Jack Erickson Product Marketing Director for RTL Synthesis Cadence Design Systems Inc.
Historically, wireload models have been inadequate for accurate modeling of wire delays. Furthermore, the inaccuracy worsens with each new process generation. Logic designers see one timing representation of their design, and physical designers see something entirely different...
Software Solution Helps Developers Enhance Security Of .NET Applications
Independent software developers who need to enhance the security of their products can now add elliptic curve algorithms, including those in Suite B, to Microsoft .NET Framework and .NET Compact Framework applications using Certicom's Security Builder API for .NET. The solution can be used with legacy as well as new applications running on multiple Windows platforms...
Though a show time change didn't have engineers packing the floor until well after noon, the Boston Embedded Systems Conference was packed yet again especially with the combination of RFID World and SD Best Practices. I walked away with scores of new products to review from all the different fields represented in Boston...
Test System Development Guide Handbook, practical advice for your test system needs
The 200 page Agilent Test-System Development Guide is a comprehensive handbook for test engineers who need to maximize test system performance and flexibility while minimizing cost and complexity. You'll find practical advice and real-world examples that illustrate the decisions and challenges involved in test system design.
The Megatronics program at the University of Texas combines mechanical, electrical, and other disciplines to provide an integrated engineering degree from previously independent disciplines and includes student projects with real-world applications.
Nineteen electronics companies joined together to launch the SOI Industry Consortium, an attempt to bring silicon-on-insulator (SOI) innovation to broad markets.
Sun Microsystems launched the first server computers based on the UltraSparc T2 chip, its newest microprocessor. Sun claims the chip is the world's fastest commodity processor, and the company is using it in servers that host Web sites and run corporate networks.
Agilent Donates $13M In EDA Software To Design Center
The new Agilent EDA Simulation Center will facilitate RF and microwave-system and circuit-design instruction and research for students. It also will serve as a catalyst for start up companies involved in wireless communications design.
Texas Instruments is working with Microsoft Corp. to help consumers store information on Microsoft's newly launched HealthVault platform. TI will allow Microsoft to bundle software on its wireless products, enabling connected consumer health devices to operate easily with the HealthVault platform.
Power Electronics Technology Exhibition & Conference
More technical Content. More exhibits. More teardowns. More of what you need to know to find the right technologies, products and components to integrate into an ever-evolving array of complex applications. From Oct. 30 to Nov. 1, the Power Electronics Technology Exhibition & Conference, held in the Hilton Anatole hotel in Dallas, Texas, will give you the tools to optimize every element of the design process:
An educational program focuses on practical, day-to-day solutions;
A full contingent of suppliers demonstrating their latest innovations in the Exhibit Hall;
And a conference schedule that hits all of the high notes - digital and portable power, power design, conversion and management, magnetics, alternative energy, LED drivers and more.
Guidelines for Mixed-Signal PHY IP Integration, Debug and Test A new Webcast presented by Electronic Design and sponsored by Synopsys 10/10/07 2PM ET
As high-speed serial interconnect IP cores such as PCI Express, SATA, and XAUI are being integrated into deep-submicron 65- and 45-nm CMOS system-on-a-chip (SoCs), a new array of design challenges are emerging not only for IP developers but also for SoC integrators. Take this opportunity to learn about a built-in self-test feature, which enables at-speed analog testing on a pure digital tester.
Send us your Ideas for Design and we'll pay you $150 for every Idea for Design that we publish. In addition, this year's top design as selected by our readers will earn an additional $500, with two runners-up each receiving $250. You can submit your Ideas for Design via e-mail to: dbs@penton.com or, mail your material to:
Ideas for Design Electronic Design 45 Eisenhower Dr., Suite 550 Paramus, NJ 07652
3G Evolution: HSPA and LTE for Mobile Broadband By Erik Dahlman, Stefan Parkvall, Johan Skold and Per Beming
Third-generation (3G) cell-phone technologies have been a long time in coming. But they are with us now and beginning to make a difference in cellular service, particularly in non-voice applications such as e-mail, Internet access, and video.
Reprints
