The push is on for IC packages in smaller form factors, not only length- and width-wise, but also height-wise. Hence, the term “3D ICs.”
Smaller form factors require greater density, and that means stacking chips and boards on top of each other in a 3D form. As ICs downsize from quad flat packs (QFPs) to ball-grid arrays (BGAs) and further down the line, fewer stacks and external I/Os are needed (Fig. 1). Many semiconductor IC experts warn that a looming interconnect crisis will emerge within a year or two, with timing delays and higher resistances in aluminum and copper interconnects caused by downward chip scaling.
Besides memory and logic, consumer electronics now integrate CMOS image sensors. Microprocessors and DSPs are sure to follow. Gigahertz and terahertz performance frequencies aren’t too far off for future consumer and other massmarket products. And when microelectromechanical-systems (MEMS) ICs join the 3D fray, packaging challenges will become even tougher.
These challenges, triggered by cramming more functions onto ever-smaller IC die, include choosing the right packaging materials, developing a cost-effective interconnect technology, determining how efficiently heat is being managed, and the growing need for better electronic-design automation (EDA) tools.
SIPS IN THE LEAD
There’s no shortage of novelties in IC packaging, with waferlevel packages (WLPs), chip-scale packages (CSPs), multichip- modules (MCMs), and multichip packages (MCPs), as well as system-in-package (SiP) and package-on-package (PoP) technologies.
According to the International Technology Roadmap for Semiconductors (ITRS), two of the most attractive approaches for 3D packaging are system-on-a-chip (SoC) and SiP methodologies. SiPs are basically MCMs with higher packaging densities and better time-to-market advantages.
W.R. Bottoms, chairman and CEO of NanoNexus, envisions packaging innovations as the answer to the difficulties that will be encountered in scaling down CMOS ICs as envisioned in Moore’s Law. Bottoms also is the chairman of the Packaging Technology Working Group for the International Electronics Manufacturing Initiative (iNEMI) Roadmap and the ITRS Roadmap for Assembly and Packaging.
Among the numerous concepts developed for 3D SiP packaging, the use of WLP has emerged as a notable trend, says Bottoms (Fig. 2). WLP allows for the packaging of both single- and multi-die devices, wherein all elements of the package are within the boundaries of the die. Also, all packaging processes are performed before a wafer is singulated into individual circuits.
SiPs don’t replace SoCs, which represent a high level of on-chip integration. Instead, they may complement each other. A complex- function SiP may contain one or more SoCs. Or based on the application, an SoC may be preferable to a SiP.
POP TARGETS CONSUMER PRODUCTS
Consumer electronics are among the biggest drivers for high-density IC packages. The PoP concept, a subset of the SiP concept, is proving attractive in this market. Typically, a PoP involves stacking discrete memory ICs and discrete logic ICs, in BGA and microBGA packages, on top of one another.
While IC manufacturers often stack IC chips of different functions into a single package, the PoP approach is valuable in terms of configuration flexibility for mobile phones, digital cameras, and PDAs. That’s because each of the PoP layers can be can be fully tested prior to stacking for greater yields in the finished product. The cost savings are key for consumer electronics applications.
Tessera Inc. honed the PoP approach via its µZ ball stacking for BGA packages (Fig. 3). IC die are placed face down on an elastomer attachment site furnished on the substrate base material and electrically connected through a rectangular slot using conventional wire bonding.
The PoP’s carrier or substrate typically extends outward beyond the perimeter of the die. This allows the substrate to accommodate the assembly of die from different manufacturers with different sizes. It also ensures compatibility with future die shrinks.
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