The latest version of Accellera’s Verilog-Analog Mixed-Signal (AMS) standard, Verilog-AMS 2.3, unifies the standard’s previous version with IEEE Std. 1364-2005, the Verilog hardware description language (HDL) standard. Verilog-AMS 2.3 enables users to develop standard and tightly integrated Verilog-AMS modules, and allows EDA software tool developers to implement EDA tools without ambiguities in the language interpretation.
Apart from IEEE-1364 integration, Verilog-AMS 2.3 introduces new analog and mixed-signal features to support and enable improved top-down AMS design and verification methodologies. These include enhancements to table_model, support for multiple analog blocks, and resolution of language conflicts with the SystemVerilog IEEE Std. P1800, such as changing the digital domain name to “discrete” from “logic,” since logic is a keyword in SystemVerilog. It also makes the usage of array literals consistent.
Accellera is an industry organization focused on electronic design automation. The new standard was approved by its board of directors and Technical Committee, made up of systems, semiconductor, and design tool companies. The next phase of Accellera’s AMS technical activities will include integration of the AMS standard with the SystemVerilog language (IEEE Std. P1800) and extensions to the AMS language for mixed-signal assertions and behavioral modeling support.
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