With a two-pronged approach, Cadence is attempting to enable designers to close the loop on low-power design. At the system level, an enhancement of the InCyte tool acquired through Chip Estimate results in greatly improved chip-level architectural power estimation. Meanwhile, an expansion of the Palladium emulation system provides for dynamic power analysis and cycle-accurate power estimation that is linked to accurate technology libraries and the synthesis flow.
Overall system power budgeting is becoming a prime consideration for designers who risk under- or over-designing the power nets in their systems-on-a-chip (SoCs). With the tool now known as the InCyte Chip Estimator, designers are able to capture power requirements at the architectural level. It’s been enhanced to perform appraisals of various power-reduction strategies against their power budget. Not only does the tool perform these what-if analyses in different functional modes, but it also illustrates how those techniques will ultimately affect die size and package selection in terms of cost savings.
The InCyte Chip Estimator is also able to drive power intent to downstream analysis and implementation tools. It captures low-power intent and automatically authors common power format (CPF) files, which, until now, was a process unsupported by any tools.
Meanwhile, an option for the Palladium acceleration/emulation system now lends the Palladium to dynamic power analysis. Simulation of high logic-switching activity is able to capture only a narrow window in time. Dynamic power analysis with Palladium, combined with RTL Compiler, allows users to calculate average power consumption over a long period of time. The system also identifies peak power windows, which can then themselves be analyzed for average power. As a result, designers can gain greater confidence in their package selection for their chip in terms of power dissipation, thus preventing over- or under-designing the package.
Lastly, Cadence is rolling out its Encounter Power System, which performs next-generation power analysis as well as power-rail-integrity analysis. The system provides a unified interface and database for timing, signal integrity, power analysis and diagnostics, enabling correct-by-construction optimization and signoff across these domains. Encounter Power System delivers a comprehensive view of timing and power integrity in the design phase. The unified database delivers fast, full-chip power grid analysis, as well as enhanced static and dynamic analysis, electromigration, thermal analysis, and statistical analyses, including on-chip power impacts from package and board parasitics.
Contact Cadence directly for pricing and delivery information.
Cadence Design Systems
www.cadence.com
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