This CMOS two-input combination NAND/NOR gate is a three-input, fourpin logic gate. A p-channel enhancementtype MOSFET (Q1) and an n-channel enhancement-type MOSFET (Q4) form one complementary connection. Q2 and Q6 form a second complementary connection, while Q3 and Q5 form the third (see the figure).
A low input at A will close Q1 and open Q4. A high input at A will open Q1 and close Q4. Similarly, a low input at B will close Q2 and open Q6, and a high input at B will open Q2 and close Q6. A low input at C will close Q3 and open Q5, and a high input at C will open Q3 and close Q5.
The output, Y, is high when Q2 is closed and either Q1 or Q3 is conducting. The output is low when Q6 is opened and Q4 and Q5 are conducting. Therefore, by forcing input B to a logic low, Q2 is always closed and Q6 is always opened, and you can use A as input 1 and C as input 2, with the gate working as a two-input CMOS NAND gate.
Output Y is also high when Q3 is opened and Q1 and Q2 are conducting. The output is low when Q5 is closed and either Q4 or Q6 is conducting. In this case, the combo gate is used as a NOR gate. Therefore, by forcing input C to a logic high (Q3 opened and Q5 closed), you can use A as input 1 and B as input 2 in a NOR gate arrangement.
Thus, this combination gate can perform both NAND and NOR operations using only four pins. If an inverter is added at the output of the gate, it can operate as an AND and OR combination gate. The logic also can be employed in a buffered version.
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