811 results found for David Maliniak, displaying items 1 - 20
October 9, 2008[TechView: EDA] Synopsys Takes The Analog/Mixed-Signal Plunge
Recognizing an opportunity to capture the hearts and minds of the expanding analog/mixed-signal (A/M-S) design community, Synopsys has launched the Galaxy Custom Designer, which takes the Galaxy design platform into the realm of fullcustom design implementation. Custom Designer has been built from scratch in an effort to carve market share from Cadence’s aging Virtuoso analog design environment. Given the push for greater integration in IC...
September 30, 2008
[Web Exclusive] ESL Platform Looks To Solidify Baseband PHY Design Flow
When it comes to the design of the physical layers of communications systems, and in particular the related algorithms, there is a paucity of design tools that are squarely focused on the tasks at hand. While there are good general-purpose math-oriented tools with which to get started on baseband algorithms, there is only a disjointed flow for designers undertaking PHY-layer development.
October 2, 2008[Ideas For Design] For Checking Software Without Hardware, FPGAs Are The Answer
An age-old truism in the system design realm is that the software is always ready to be checked out before first ASIC silicon is in hand. This leaves the members of the design team with an equally ageold conundrum: How are they to verify their first crack at an application stack and associated drivers without hardware to run them on? Waiting until that first silicon comes from the fab is an uncomfortable and often untenable option. The answer,...
September 25, 2008[TechView: EDA] Tools Take On IC-Package And SiP Design Challenges
In surveying customers, Cadence found four key challenges facing designers of IC packages and systems-in-package (SiPs). Ambitiously, the company seeks to address them all in its SPB 16.2 release of the Allegro printed-circuit board (PCB) and IC packaging/SiP flows, which delivers advanced IC package/SiP miniaturization, design cycle reduction, and DFM-driven (design for manufacturing) design, along with a new power integrity modeling...
September 16, 2008
[Web Exclusive] Visions Of The Future (Part 1): A Ubiquitous Cloud Of Computing
A vastly different information technology (IT) landscape awaits us in the not-too-distant future, one marked by a world of ubiquitous computing that “will change the way we think about IT.” Such was the vision outlined by Dr. Jan Rabaey of the University of California at Berkeley in a keynote address delivered at last week’s CDNLive! Silicon Valley, the latest in Cadence Design Systems’ worldwide series of user conferences.
September 16, 2008
[Web Exclusive] Visions Of The Future (Part 2): Look East, Electronics Industry, Look East
Just when you think the party’s over for the electronics industry, along comes another prediction for a rosy growth-filled future. This one, however, came fueled by a compelling blizzard of statistics showing that the industry must look to the emerging, and technology-hungry, societies of the Pacific Rim and Asia. So went a keynote address from Walden C. “Wally” Rhines, CEO of Mentor Graphics Corp., at last week’s EDA Tech Forum in Santa Clara.
September 16, 2008
[Web Exclusive] Process Design Kit Targets Analog/Mixed-Signal Products
The latest revision of austriamicrosystems’ analog/mixed signal high performance process design kit (“HIT-Kit”) is now available for its 0.35-?m CMOS, high-voltage CMOS, and SiGe-BiCMOS specialty technologies. Based on the latest version of Cadence’s Virtuoso custom design platform (IC 6.1 release), the HIT-Kit v4.0 is said to significantly improve time to market for products in the analog/mixed-signal arena.
September 16, 2008
[Web Exclusive] Open Verification Methodology Sprouts Hierarchical Guidelines
The latest version of the Open Verification Methodology (OVM) provides a new OVM User Guide, which contains step-by-step guidelines to help users develop reusable, interoperable verification IP and hierarchical environments to facilitate plug-and-play verification.
September 11, 2008[Engineering Essentials] Verification Evolves Into Lean, Mean Bug-Stomping Machines
We all want our next-generation Pocket Rocket to do new stuff (and do the old stuff better), as well as get smaller, run longer, and cost less. We also don’t necessarily want to wait for the holiday season for it to hit the shelves. We gadget freaks are often rather impatient in that regard. For the design team, these marketplace realities don’t exactly lead to a leisurely existence. Instead, it means negotiating the extraordinary challenges of making it all...
August 28, 2008[Leapfrog: First Look] 45-nm Via-Programmable ASICs Add High-Speed I/O Transceivers To Feature Mix
ASIC design starts have plummeted in recent years, and there are many good reasons why. Designs at ultra-deep-submicron process nodes are awfully expensive and getting more so daily as mask costs rise, software content proliferates, and verification takes longer. Meanwhile, the steady rise of application-specific standard products (ASSPs) has also contributed heavily to the ASIC’s marketshare slide. Thus, many designers have turned to alternative...
August 14, 2008[TechView: EDA] Model Extractor For CMOS Sports Improved RF/DC Parameters
It’s very difficult to create accurate device-simulation models for advanced CMOS digital processes. Why? Because hard-to-model effects like gate accumulation and tunneling, trap-assisted tunneling, and halo effects have become so prevalent at ultra-deep-submicron technology nodes. For designers of RFcapable systems-on-a-chip (SoCs), this has become a critical issue in the accurate prediction of the behavior of highly nonlinear RF circuits,...
July 14, 2008
[ED Bookstore] BGA Breakouts & Routing
Call it a “vanity” publishing project if you will, but Charles Pfeil’s book, BGA Breakouts & Routing, published by his employer, Mentor Graphics, is more than worth the price of admission. Pfeil, who is the engineering director of Mentor’s System Design Division, is an acknowledged industry expert in the black art of printed-circuit board (PCB) routing, and he brings his expertise to bear on this densely-packed and richly-illustrated volume.
July 10, 2008[Engineering Feature] Hardware/Software Co-Design Comes Of Age
There once was a time when system design was completely serial. Entire hardware platforms were designed, prototyped, debugged, and virtually completed before any software development began. Of course, such methodologies corresponded to the days of much broader market windows. The very idea of such a quaint approach is enough to make one snicker. Today, itâ??s quite different. Those market windows have narrowed to a sliver. Hardware development typically lags...
June 24, 2008
[TechView: EDA] Formal Verification Suite Takes In Wider View Of Designs
If there’s ever been a knock on formal verification, it’s the amount of time it takes to do a formal run on a full design. Formal tools can only take in so much design data at a given time, forcing design teams to partition the design for formal analysis. Sure, it’ll find bugs that can’t be found any other way, but it can take quite a while to accomplish. In the latest revision of its flagship tool, JasperGold, Jasper Design Automation has made...
June 16, 2008
[Design Automation Conference] A 45th DAC Post-Mortem
Last week’s 45th Design Automation Conference (DAC) in Anaheim was my twelfth consecutive DAC, and it was surely the most interesting and different I’ve experienced in journalistic terms. Yeah, that was me traipsing around the show floor with my colleague Damian Mendez in tow, toting a great big video camera. It was my first experience in documenting DAC in video, and I would term it a success.
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