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EDA Alert
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308 results found for EDA Alert, displaying items 1 - 20
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July 15, 2008
EDA Alert: July 15, 2008
Hardware/Software Co-Design Comes Of Age
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John Arkontaky
, et al.
July 1, 2008
EDA Alert: July 1, 2008
A Mid-Year Check On The Optimism Meter
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John Arkontaky
, et al.
June 17, 2008
EDA Alert: June 17, 2008
A 45th DAC Post-Mortem
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John Arkontaky
, et al.
June 3, 2008
EDA Alert: June 3, 2008
45th DAC Takes The SoC Methodology Plunge
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David Maliniak
May 20, 2008
EDA Alert: May 20, 2008
Go To DAC, For Your Career's Sake . . .
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David Maliniak
May 6, 2008
EDA Alert: May 6, 2008
Software Rules The Day In Multicore SoC Design
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David Maliniak
April 15, 2008
EDA Alert: April 15, 2008
"You say you want a revolution? Well, you know . . . we all want to change the world."
John Lennon penned that opening line of The Beatles' "Revolution" in 1968. And it's just as relevant now as it was 40 years ago. The electronics industry stands on the threshold of an era of creative innovation as it rushes toward multicore system-on-a-chip (SoC) design.
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David Maliniak
April 1, 2008
EDA Alert: April 1, 2008
Now that there are two competing industry formats to capture power intent for low-power designs—the Common Power Format (CPF) and the Unified Power Format (UPF)—design teams need to understand the similarities and differences between the two.
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David Maliniak
March 18, 2008
EDA Alert Update: March 18, 2008
Verifying the integration and operation of new IP in a legacy system-on-a-chip (SoC) becomes challenging. This is true particularly when the legacy SoC environment was built using a directed test methodology and validation of new IP requires corner case stimulus to achieve required functional coverage.
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David Maliniak
March 4, 2008
EDA Alert Update: March 4, 2008
A crisis of critical proportions is emerging as more and more IC designs demand a complex mix of digital and analog functionality to meet cost, size, packaging, power, and price considerations. This is a switch: in the past, most chips have been either digital or analog.
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David Maliniak
February 19, 2008
EDA Alert: February 19, 2008
Unlike so many of my colleagues within the EDA industry, I'm optimistic about 2008. That's because the emulation market sector is on the rise and I believe we could see double-digit growth in this sector. Yes, I'm defying the paltry 2% growth some EDA executives have forecast for the entire industry.
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David Maliniak
February 5, 2008
EDA Alert: February 5, 2008
Closer, more coordinated interaction between IC design and manufacturing teams is the key to improving product yield. Although many IC manufacturers are trying to institute true design for manufacturability (DFM), more effective collaboration with their design counterparts is necessary to overcome numerous issues that impede success.
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David Maliniak
January 22, 2008
EDA Alert: January 22, 2008
Over the past few years, the "power problem" has registered more strongly on the radars of system design teams. Portable and handheld consumer electronics keep shrinking, and hence so do their batteries. In 2008, it's all about power for EDA, in terms of tools, methodologies, and even standards. There will be a spate of announcements having to do with low-power design in the next year or two spanning all those areas...
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David Maliniak
January 8, 2008
EDA Alert: January 8, 2008
In an effort to further improve the Open Core Protocol's (OCP's) ability to speed IP integration, the OCP International Partnership has opened its new debug specification to member review. The specification details an approach to a standardized OCP bus-compliant debug interface.
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David Maliniak
December 18, 2007
EDA Alert: December 18, 2007
Design complexity has reached a point where RTL is no longer a viable starting point for verifying most silicon systems. RTL design optimization and simulation has become so time-consuming that they now threaten product schedules. However, new methodologies like transaction-level modeling (TLM) are emerging to support faster verification and design feedback.
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David Maliniak
, et al.
December 4, 2007
EDA Alert: December 4, 2007
Two changes will occur in manufacturing test products in response to market pressures: embedded compression tools and logic built-in self test (LBIST) will converge; and manufacturing test tools will be integrated with yield and failure-analysis tools and looped back into design tools to improve yield for ICs at 65 nm and below.
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David Maliniak
, et al.
November 26, 2007
EDA Alert: November 13, 2007
Even as leakage overwhelms their power budgets, IC design teams are finding ways to plug the holes that are costing them dearly at sub-micron nodes...
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David Maliniak
, et al.
October 30, 2007
EDA Alert: October 31, 2007
Historically, wireload models have been inadequate for accurate modeling of wire delays. Furthermore, the inaccuracy worsens with each new process generation. Logic designers see one timing representation of their design, and physical designers see something entirely different. This discontinuity impacts the success of the project in several ways...
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David Maliniak
October 16, 2007
EDA Alert: October 16, 2007
Acquisitions by EDA companies are a fact of life. Even in the worst of times, not a year goes by without a raft of them. In fact, Synopsys, Mentor Graphics, and Cadence are the result of countless mergers over the years. While the large companies do occasionally turn out innovative internally-produced products, their new technology more typically comes from startups they've acquired...
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David Maliniak
September 25, 2007
EDA Alert: September 25, 2007
Some years ago, a prestigious investment firm ran television commercials in which a distinguished British actor proclaimed that "they make money the old-fashioned way. They earn it." In a similar vein, it'd be nice if it could be said of us electrical engineers that "we solve problems the old-fashioned way. We think." Unfortunately, we electrical engineers tend to be victims of our own success in that we're over-dependent on computers to do our analysis and measurements for us...
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David Maliniak
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