1146 results found for Web Exclusive, displaying items 1 - 20
September 30, 2008
ESL Platform Looks To Solidify Baseband PHY Design Flow
When it comes to the design of the physical layers of communications systems, and in particular the related algorithms, there is a paucity of design tools that are squarely focused on the tasks at hand. While there are good general-purpose math-oriented tools with which to get started on baseband algorithms, there is only a disjointed flow for designers undertaking PHY-layer development.
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David Maliniak
September 23, 2008
Establishing A New Frontier In Embedded Multicore Programming
Over the last few years, the electronics industry has seen a varied range of exotic new multicore processor architectures, 54 at our last count. While many of the inventors of these fascinating devices have promoted them as general solutions, only a few have seen success, and then in very specific application spaces.
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David Stewart
September 16, 2008
Debugging SoCs Is More Complex Than Finding A Needle In A Haystack
Do you remember 1964? That’s when Motown Records’ The Velvelettes, backup singers for Martha Reeves and the Vandellas, cheekily sang,“‘cause finding a good man, girls, is like finding a needle in a haystack.” The song offers refreshingly sound advice 48 years later as the singers intone, “You’d better get yourselves on the right track.” It seems that these days finding a bug in a system-on-a-chip (SoC) design has become significantly tougher than searching for a good man was in 1964.
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Lauro Rizzatti
September 16, 2008
Visions Of The Future (Part 1): A Ubiquitous Cloud Of Computing
A vastly different information technology (IT) landscape awaits us in the not-too-distant future, one marked by a world of ubiquitous computing that “will change the way we think about IT.” Such was the vision outlined by Dr. Jan Rabaey of the University of California at Berkeley in a keynote address delivered at last week’s CDNLive! Silicon Valley, the latest in Cadence Design Systems’ worldwide series of user conferences.
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David Maliniak
September 16, 2008
Visions Of The Future (Part 2): Look East, Electronics Industry, Look East
Just when you think the party’s over for the electronics industry, along comes another prediction for a rosy growth-filled future. This one, however, came fueled by a compelling blizzard of statistics showing that the industry must look to the emerging, and technology-hungry, societies of the Pacific Rim and Asia. So went a keynote address from Walden C. “Wally” Rhines, CEO of Mentor Graphics Corp., at last week’s EDA Tech Forum in Santa Clara.
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David Maliniak
September 16, 2008
Process Design Kit Targets Analog/Mixed-Signal Products
The latest revision of austriamicrosystems’ analog/mixed signal high performance process design kit (“HIT-Kit”) is now available for its 0.35-?m CMOS, high-voltage CMOS, and SiGe-BiCMOS specialty technologies. Based on the latest version of Cadence’s Virtuoso custom design platform (IC 6.1 release), the HIT-Kit v4.0 is said to significantly improve time to market for products in the analog/mixed-signal arena.
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David Maliniak
September 16, 2008
Open Verification Methodology Sprouts Hierarchical Guidelines
The latest version of the Open Verification Methodology (OVM) provides a new OVM User Guide, which contains step-by-step guidelines to help users develop reusable, interoperable verification IP and hierarchical environments to facilitate plug-and-play verification.
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David Maliniak
September 8, 2008
CTIA Comes To The City By The Bay
The cellular industry is so hot right now, CTIA can’t contain all of its advances in just one show. This week, the Wireless Association presents its second event of the year at the Moscone Center in San Francisco. With 10,000 attendees expected, this follow-up to April’s Las Vegas show and February’s Mobile World Congress in Barcelona will focus on the IT and entertainment sides of the business.
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Louis E. Frenzel
September 8, 2008
Cadence Comes At Power From Two Perspectives
With a two-pronged approach, Cadence is attempting to enable designers to close the loop on low-power design. At the system level, an enhancement of the InCyte tool acquired through Chip Estimate results in greatly improved chip-level architectural power estimation. Meanwhile, an expansion of the Palladium emulation system provides for dynamic power analysis and cycle-accurate power estimation that is linked to accurate technology libraries and the synthesis flow.
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ED News Staff
September 5, 2008
Chip Companies Team Up On Tech Deals
Joint ventures and technology deals have been the theme for some of Europe’s biggest chip makers this Olympic summer, with Munich-based Infineon taking the gold medal and STMicroelectronics (ST) coming in a close second with silver. ULIS and Renesas Technology Europe also placed well, with their own advances in sensors and power MOSFETs, respectively.
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Paul Whytock
September 2, 2008
Engineering A Hall Of Famer
Once a year we at Electronic Design ask our readers to stand up and recognize those who have made major contributions to the electronic engineering world. Our “2008 Electronic Design Hall of Fame” is primed to hoist another class of engineer superheroes onto your proverbial shoulders.
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John Arkontaky
September 2, 2008
Collaboration Results In First IEEE 1149.7 cJTAG Semiconductor IP Core
The industry’s first synthesizable IP core that implements the upcoming IEEE 1149.7 cJTAG standard, which will be ratified in early 2009, is available from IPextreme. The IEEE 1149.7 standard will provide designers with powerful extensions to the current IEEE 1149.1 (JTAG) standard, using fewer pins and maintaining compatibility...
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ED News Staff
August 29, 2008
Yield Enhancement Software To Aid Solar Cell Fabs
Magma Design Automation Inc. is developing a yield enhancement software system customized for solar fabs to improve conversion efficiency, increase yield and reduce the manufacturing costs of solar cells. Magma is collaborating with Pegasus Semiconductor-Solar to refine product specifications and test the new product, based on Magma’s YieldManager software system.
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ED News Staff
August 29, 2008
Audio Engine Codec Library Expands With Dolby Pro Logic Additions
Tensilica’s audio codec library for its Xtensa HiFi 2 Audio Engine has been expanded to include Dolby Pro Logic II and Pro Logic IIx decoders. Both Dolby Pro Logic decoders are essential sound processing technologies employed in home-theater AV receivers. Dolby Pro Logic II creates 5.1-channel surround sound from any stereo movie, music, TV, or game audio source, while Dolby Pro Logic IIx extends the sound experience up to a full 7.1-channel configuration.
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ED News Staff
August 29, 2008
Accellera Rolls New Version of Analog, Mixed-Signal Standard
Accellera’s Board of Directors and Technical Committee members have approved a new version of its Verilog-Analog Mixed-Signal (AMS) standard, Verilog-AMS 2.3, as an Accellera standard for analog and mixed-signal design and simulation. The new Verilog-AMS standard unifies the Verilog-AMS 2.2 specification with the IEEE Std. 1364-2005 or Verilog hardware description language (HDL) standard.
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ED News Staff
August 19, 2008
DNA In Your Gadgets?
We all know how DNA technology has revolutionized forensics as the unique identifier for organic life. Now here comes DNA technology for automobiles, motorcycles, marine equipment, clothing, laptops, building materials, packaging, industrial goods, construction equipment, etc.
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Roger Allan
August 18, 2008
User Advisory Group To Guide Open Verification Methodology’s Evolution
The best cooperative efforts in the EDA industry are guided by the collective input of users and technology providers. Those that aren’t tend to be dominated by one or two key players, making them somewhat less than truly cooperative. The Open Verification Methodology (OVM) World community is striving for the former path through its establishment of the OVM Advisory Group (OAG), an organization of distinguished users and ecosystem suppliers.
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ED News Staff
August 18, 2008
DDR3 and DDR2 Memory IP Bolsters SoC Designs
A full range of DesignWare DDR intellectual property (IP) is available for systems-on-a-chip (SoCs) that require an interface to high-performance DDR3, DDR2, and DDR memory subsystems. The DesignWare DDR IP delivers memory system performance of up to 1600 Mbps, which is the maximum data rate of the JEDEC DDR3 specification. The IP includes configurable protocol and memory controllers, integrated mixed-signal PHYs including I/Os, and verification IP.
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ED News Staff
August 18, 2008
PCB Tools Cross-Probe Between Layout And Schematic
Providing a valuable mechanism for design, review, verification, and testing of printed-circuit board (PCB) designs, CircuitSpace Foundation from DesignAdvance Systems now offers cross-probing between layouts and PDF schematics. The new cross-probing capability adds to CircuitSpace’s existing auto-clustering and replication technologies and works seamlessly within Cadence’s Allegro PCB design environment.
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ED News Staff
August 18, 2008
Constraint-Driven Flow Targets PCB High-Density Interconnects
With pin pitches shrinking on FPGAs and other IC packages, many printed-circuit board (PCB) designers—like it or not—are forced to enter the realm of high-density interconnects (HDIs). In response to this trend, Cadence has announced the SPB 16.2 release of its Allegro and OrCAD families of PCB design flow. While the flow has offered constraint-driven design for some time, that capability is now coupled with new features aimed at HDIs.
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ED News Staff
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