Electronic Design

1.5-Bit Stages In Pipeline ADCs

High-speed pipelined ADCs can take advantage of basic 1.5-bit stages to enhance performance and suppress cost.

Use of pipeline analog-to-digital converters (ADCs) continues to expand, both as standalone parts and as embedded functional blocks in system-on-a-chip (SoC) ICs. They boast acceptable resolution at high-speed operation and can be integrated onto relatively small die area. Driven by IC chip cost factors, many commodity CMOS-technology SoCs now include embedded pipeline ADCs.

Pipelined converters attain their final resolution through a series cascade of lower-resolution stages. For example, a 12-bit converter could be a cascade of four 3-bit stages. Most engineers are comfortable with the basic concepts of a 3-bit flash ADC stage. However, the 1.5-bit stage also is used extensively, despite the fact that its characteristics and advantages are less widely known.

Pipeline ADCs consist of a series of stages that are isolated by sample-andhold (S/H) buffers. The stages work concurrently. The first stage operates on the most recent sample, while the following stages operate on analog remainder voltages, called residues from previous samples.

Because the stages work simultaneously, the number of stages used to obtain a given resolution (e.g., 12 bits) isn't constrained by the required throughput rate (e.g., 20 Mbits/s). The stages can be designed, among other factors, to minimize die area.

A consequence of multistage concurrent operation is latency, meaning delay. The output code for a given sample isn't obtained until a number of clock cycles later. Latency isn't considered to be a problem in many applications.

Figure 1 shows a block diagram of a general pipelined ADC with M stages. For every stage, there's a S/H, a low-resolution ADC, a low-resolution digital-to-analog converter (DAC), a subtracter, and a controlled gain amplifier.

Each stage samples and holds the output from the previous stage. The held input is converted into a low-resolution digital code by the ADC, and then back to analog by the DAC. The DAC output is subtracted from the held input, and the difference is amplified to produce an output residue voltage that's passed to the next stage.

In general, the amplification corresponds to the resolution of the stage to use the full voltage range available. For example, a 3-bit stage would have an amplification of 8. The amplifier can be placed either in front of, or following, the subtracter.

For high-speed converters, there's an advantage to minimum stage resolution. It minimizes the required interstage gain, which in turn maximizes bandwidth, since gain-bandwidth is a constant for a given technology. This factor is particularly important for parts made using a cost-effective commodity CMOS wafer-fabrication process, as maximum achievable speed is required from critical circuit blocks such as operational amplifiers.

Assume symmetrical reference voltages of ±VREF. The minimum possible stage resolution (and maximum bandwidth) of 1 bit would place an analog decision level midway between the reference voltages—that is, at ground. The amplifier would have a gain of 2.

A 1.5-bit stage is a 1-bit stage into which some redundancy is built to provide a large tolerance for component tolerances and imperfections. A digital correction algorithm later eliminates the redundancy. A 1.5-bit stage is actually a stage that represents approximately 1.5 bits.

The 1.5-bit stage uses two symmetrical analog comparison levels, VH and VL, instead of one (Fig. 2a). The amplifier has a gain of 2. Choice of voltage levels VH and VL isn't critical, but because of the following gain of 2, they must lie within the range of -VREF/2 and +VREF/2.

Allowing for circuit imperfections to be corrected by the digital correction algorithm, VH is usually in the range 0.2 VREFHREF. A common choice is VH = 0.25 VREF and VL = -0.25 VREF. The 1.5-bit configuration holds an advantage in that there's no analog decision level or trip point at mid-range, which benefits low-signal-level operation.

The operating voltage range is divided into three sections: High (H) above VH, Mid (M) between VH and VL, and Low (L) negative of VL. This system is known as Redundant Signed Digit (RDS) because the High range was originally tagged as +1, Mid range as 0, and Low range as -1. Table 1 lists summary information about the 1.5-bit stage configuration.

The stage low-resolution ADC comprises two comparators plus some simple encoding. The ADC output consists of two bits—B1 and B0. This is the initial digital output, before code conversion and error correction. The output codes are 00, 01, and 10 for VIN in the L, M, and H input ranges, respectively. The DAC outputs are -VREF, 0, and +VREF for VIN in the L, M, and H input ranges. The analog residue voltages out of the stage after subtraction are:

For: Residue is:

Figure 2b shows the stage VOUT/VIN transfer function, which is highly nonlinear, for VH = 0.25 VREF and VL = -0.25 VREF.

A basic voltage-dividing resistor string typically creates the reference voltages. For CMOS circuitry, this is the most critical use of resistors. All other high-accuracy operations, such as the x2 amplification, are performed using capacitor ratios.

Although circuit alternatives exist, the S/H, DAC, subtraction, and x2 amplifier generally can be combined in a multiplying DAC functional block (MDAC). Operation is via charge transfer using a common capacitor array.

One of the most demanding design areas involves the operational amplifiers of the S/H and the x2 amplifier. One design technique includes doublecascode current mirrors to maximize input stage load impedance and, therefore, gain. Another is to use commonmode feedback loop biasing circuits to optimize bias levels and, therefore, available output voltage swings for relatively low supply voltages. Operational-amplifier frequency response also must be maximized, which is a demanding design challenge, particularly if a commodity CMOS-process technology is being used.

Each 1.5-bit pipelined ADC stage, as described earlier, produces a 2-bit code. Once the error-correction algorithm is applied, this is reduced to the final one-bit-per-stage code. Even in the absence of any errors at all, the 2-bit-per-stage code must be converted to 1 bit per stage.

Many sources of possible error exist in the involved circuitry. These include offset voltages in the comparators and amplifiers, gain error of the x2 amplifier, amplifier settling time, converter nonlinearities, capacitor voltage dependency, and a host of others.

All of these shift the ideal stage transfer function of Figure 2b in some amount and direction. Many of these are corrected, or at the very least substantially improved, by the error-correction procedure. For example, offset voltage effects are fully corrected.

An uncorrected error source is gain error of the x2 amplifier. Primarily due to an error in 2:1 capacitor ratio, it's a critical issue in 1.5-bit stages. The capacitor ratio of the first stage is the most important one, since the error there appears at the output multiplied by the gains of all the following stages.

An example illustrates these issues, including error-correction code conversion. Figure 3 shows a three-stage cascade of 1.5-bit stages in block diagram form, accompanied by Table 2.

Because the resolution is 3 bits, the input voltage range of ±2 V is divided into eight equal sectors as shown in the first column of Table 2. The intended output code is binary increasing from negative to positive, as shown in the second column, which is labeled design output code.

The third column of Table 2 lists arbitrarily selected input voltages, one in each of the eight equal input-voltage sectors. The residue voltages of the first two stages are shown, as are the three sets of two-digit uncorrected output codes from each of the three stages.

To generate the final code-converted and error-corrected 3-bit output code from the three 2-bit stage codes, the 2-bit digital outputs from each stage are added together with 1 bit overlapped between adjacent stages. The three MSBs are the final code. For the VIN = 0.79 V example, the output codes from the three stages are 10, 01, 00. The final 3-bit output code is obtained as follows:

1 0    
  0 1  
    0 0

1 0 1 0

Ignoring the far-right digit, the final output code is 1 0 1.

The full set of final output codes in Table 2 is obtained in the same way. This error-correction algorithm can be implemented with a series connection of adders, or alternatively using logic.

Code conversion and error correction in RSD pipeline converters is a more substantial area than the foregoing simple example might suggest, and one in which clear comprehensive literature is in short supply. Also, pipeline ADCs aren't typically-made up of only 1.5-bit stages. For example, a 10-bit converter might be a 3-bit flash first stage followed by five 1.5-bit stages ending in a 2-bit flash stage.

Though these descriptions have been in terms of single-ended circuitry for clarity, most pipelined ADCs with 1.5-bit stages are fully differential systems. Another important issue, not addressed here, is clocking and the synchronization of the data output circuitry.

To sum up, 1.5-bit stages in highspeed pipelined ADCs have become established as both performance and cost-effective circuit blocks. They're straightforward in concept, at least in terms of their basic operation.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.