Electronic Design

ADC Arrays For Beam-Forming Applications

Sponsored by: ANALOG DEVICES

What kinds of applications use large arrays of analog-to-digital converters (ADCs)?
Phased-array radar systems and medical imaging are two major application areas. Many of these applications place common demands on the ADCs and the analog front ends (AFEs) that drive them, particularly in terms of noise performance, power consumption, and pin count.

How are those apps alike?
The core concept is beam shaping. While radar designers developed the "phased array" idea of steerable beams, engineers who design medical X-ray, magneto-resonant, and ultrasound equipment have expanded it. Today, these systems are some of the most sophisticated applications (see the figure).

How do the signal-processing components of ultrasound systems work?
Signals are attenuated as they travel more deeply into the patient, so the field being imaged is divided up into planes. Each successive plane gets higher transmit energy. On the transmit side, a beamformer that controls the delay pattern and pulse train determines the desired transmit focal point. The amplifiers that drive the transducers then amplify the beamformer's outputs.

In each receive signal channel, the first element is a T/R switch that blocks the high transmit voltage pulses. This is followed by a low-noise amplifier (LNA) and variable gain amplifier (VGA), which implement a time-gain control (TGC). Sometimes there are also apodization functions (spatial "windowing") to reduce beam side lobes. If the ultrasound unit also includes Doppler signal processing to measure blood flow, a separate channel carries the data.

The transducer cable contains 48 to 256 channels, each with its own micro-coaxial cable. (Soon there will be 3D ultrasound with 512 or more input channels.) In most ultrasound gear, there are separate transducer arrays in the head for different types of scan. In these arrays, each transducer element directly drives one cable in the cable bundle. Noise figure is affected by both cable losses and losses in the relay that selects among different heads.

What are the challenges in AFE design?
Signal attenuation is one of the toughest aspects of AFE design. At 5 cm, a 10-MHz ultrasound signal is attenuated by 100 dB. Add an instantaneous dynamic range of about 60 dB, and the total dynamic range required is 160 dB.

That's why ultrasound uses so many channels. It takes a combination of time-gain control, channel summation, and filtering to produce good images. Also, Boltzman noise arises from the transducer and the human body, and it's complicated by cable capacitance.

Several generations of ADCs have been optimized for ultrasound. Generation one used a ladder attenuator and an external LNA. Generation two integrated the LNA, but needed dual supplies for noise performance. Generation-three ADCs use single +5-V supplies (with differential inputs to optimize dynamic range), integrate the LNA, and cut power use almost by half. They're also designed for fast recovery from T/R-switch overload.

What are the data-conversion design challenges?
Beamforming is the function in which ADC performance is perhaps most critical. Received pulses from each focal point are stored and then lined up and coherently summed. This provides spatial processing gain because the noise of the channels are uncorrelated.

In digital beam forming (DBF), the signal is sampled as close to the transducer elements as possible. Then, the signals are delayed and summed digitally. DBF requires many high-speed and high-resolution ADCs. ADC makers try to keep that power as low as possible while providing dynamic range and a usable sample rate.

How can system designers handle the I/O from all those ADCs?
Serializing the ADC outputs is the obvious answer. Less obvious is the fact that while standard ANSI-644 low-voltage differential signaling (LVDS) is possible, IEEE Std 1596.3 offers lower power consumption. 1596.3 is an extension to the Scalable Coherent Interface (SCI) standard. It defines a lower-voltage differential signal—down to 250 mV—and encoding for SCI packets. An SCI interface chip on the board with the FPGA that does the signal processing handles deserialization.

One caution: SCI sends data on both clock edges, and ADCs that use both clock edges to generate internal timing signals may be sensitive to clock duty cycle. Some recent ADCs include a duty cycle stabilizer (DCS) that retimes the non-sampling edge, providing an internal clock signal with a nominal 50% duty cycle.

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