Amid the fervor to move the next generation of microprocessors, memories, and other digital circuits to 0.13-µm CMOS production lines this year, analog and mixed-signal IC suppliers are racing to adopt 0.25-µm design features. They're trying to narrow the gap between digital and analog CMOS that has existed from day one.
In the early 1990s, this gap was so wide that it seemed analog designers would take forever to come closer to their digital counterparts in ex-ploiting the latest ad-vances in CMOS pro-
cesses. But in the last few years, developers of analog and mixed-signal devices have made significant strides and have moved forward on the scaling ladder. A plethora of papers presented at the recent International Solid-State Circuits Conference (ISSCC) is testimony to that trend.
Only a few years ago, designers of op amps, comparators, data converters, and other mixed-signal chips were struggling to migrate to 0.5-µm CMOS design rules. To go from 0.8-µm CMOS features to 0.5-µm or 0.6-µm geometries was a major step forward. All the while, digital circuit designers were basking in the glory of sub-0.2-µm feature sizes with a roadmap that showed processors approaching sub-0.1-µm (or nanometer) CMOS design rules by 2003. In contrast, major analog and data-converter IC makers were migrating to 0.5-µm CMOS processes for high-performance solutions.
Today, the analog scenario is quite different. The same analog designers who were unsure of scaling to deep-submicron CMOS territory are now optimistic about narrowing that margin. They're combining process and circuit techniques to take full advantage of smaller transistor sizes, lower voltages, higher signal speeds, and lower power consumption. In addition, there's an extra cost benefit that comes with the reduced die size.
Designs based on 0.35-µm CMOS are already in the mainstream production phase, and new circuits are under development to tap 0.25-µm and finer gate lengths. In fact, STMicroelectronics, a major data-converter supplier, has already implemented a pipelined 10-bit, 50-Msample/s analog-to-digital converter (ADC) in 0.25-µm CMOS with satisfactory spurious-free dynamic-range (SFDR) performance and other ac characteristics. Motivated by the exploding markets for handheld cellular and wireless Internet gadgets, this Franco-Italian chip maker is talking about volume production of its 0.25-µm ADC design.
Meanwhile, other major players are readying 0.25-µm CMOS converter circuits as well. Several papers at this year's ISSCC sent a similar signal that analog and data-converter designers are poised to reap the benefits of smaller CMOS transistors. For example, researchers at Philips Research Labs in Eindhoven, The Netherlands, crafted a calibrated two-step, 12-bit, 54-Msample/s ADC in 0.25-µm CMOS. Developers at Texas Instruments have forged a 100-MHz, 10-bit ADC using 0.18-µm CMOS. Two presentations on CMOS voltage-controlled oscillators (VCOs), one from Katholieke University in Leuven, Belgium, and the other from Bell Labs in Murray Hill, N.J., demonstrated that fully integrated microwave and millimeter-wave VCOs can be built using 0.25-µm CMOS. Furthermore, mixed-signal design company Antrim Design Systems has created data-converter IPs based on 0.25-µm CMOS with a migration path to finer geometries.
But, will the twain meet on a common CMOS platform? What will it take to accomplish that goal, and by what time frame? Send me your thoughts.