Electronic Design

Analog/Mixed-Signal> High-Speed DAC Designers Face Tall Hurdles In A Digital World

Current application trends have caused a chain reaction in the design requirements of high-speed digital-to-analog converters (DACs), dictating the challenges faced by analog designers. The need for greater processing speed has designers craving smaller device geometries. Smaller devices provide higher packing density and lower overall power consumption, due to lower parasitics and lower supply voltages. Such a reduction in device breakdown voltages that accompany the smaller geometries imposes these lower supply voltages.

In addition to design requirements, most DAC designs are integrated into larger digital chips. Thus, designers must operate within new process constraints. The combination of application needs and digital design processes introduces serious challenges for today's DAC designers.

Purely analog components are still designed on larger geometry processes or customized medium geometry processes. One result is that reduced voltage headroom shrinks the size of signals that can be generated and processed, along with the allowable gate drive. Therefore, for a given device size, the highest speed is obtained by maximizing the bias point. This maximizes the transconductance, while the parasitics remain constant. Lower gate drive will then lower the available transconductance of transistors.

Another challenge in DAC designs with reduced supply voltages is that lowering supply voltage diminishes the designer's ability to use cascoding to improve overall circuit gain and matching. Cascoding of devices on a current string is the best method of improving matching when differences in drain or collector voltages exist. It's critical to producing accurate current mirrors and binary-weighted current strings, which are at the core of most high-speed DAC designs. At the same time that designers lose the ability to cascode devices, the output transconductance of the basic transistors rises because of decreased channel lengths, which creates more of a need for cascoding.

Device matching also degrades with smaller geometries. To tackle all of the matching and accuracy concerns of DACs, designers can rarely use minimum-sized devices. Consequently, digital designs strongly benefit from process shrinks. But analog designs, at voltages below 3 to 5 V, gain little benefit—and actually suffer from process shrinks.

The future may help these analog design challenges if, as in the past, the analog functions are "disintegrated" from the digital. If this happens, designers should see new DAC designs that require high-speed serial interfaces, which could run at speeds well above 1 GHz.

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