AWR Unveils Next-Generation Analogue And RFIC Design System

Applied Wave Research, the high-frequency EDA tools company, has launched Analog Office 2004 software for next-generation analogue and radio frequency integrated circuit (RFIC) designs. This latest version, which AWR claims is the first complete IC design system in over a decade designed and optimised from the ground up for designers of analog and RF ICs, has been enhanced to provide a unified design environment. The Analog Office 2004 toolset spans the complete IC design flow, from system-level to circuit-level design and verification, for entire top-to-bottom and front-to-back high-frequency design.

New in the toolset is: support for the Linux platform, an extension of the AWR Intelligent Net (iNet) technology to handle arbitrary layout geometries; automatic and 'on the fly' connectivity extraction in layout; support for Verilog-A analogue behavioural language; integration of an additional SPICE circuit simulator and electromagnetic (EM) simulators and support for industry standard physical verification flow for final chip tape-outs.

'The complexity of today's new technologies renders traditional design methods inadequate in terms of accuracy, efficiency and cost. An entirely new EDA approach is required in order to ensure complete design closure between IC, package, module, and PCB design phases,' explained James Spoto, AWR president and CEO. 'The Analog Office design system provides the ability to achieve optimum RF closure through a unified data model and single design environment encompassing all of the design domains.'

RF closure and unified data model
The high-frequency impairment challenges in today's complex RFICs are forcing the need to obtain 'RF closure' between the RFIC's system and circuit, electrical and physical, and design and test activities before commitment to costly IC implementation. The Analog Office design system achieves this, says the company. The AWR Design Environment is built on an open standards-based software platform enabling easy integration of tools to capture, synthesise, simulate, optimise, layout, extract and verify designs in all domains. This protects customers' investment in models and simulators, lowers their cost of support and helps easy customisation of specific flow requirements.

The Analog Office unified design environment interacts with a set of integrated tools, including:

  • easy-to-use graphical user interface (GUI) supporting
  • system-level and circuit-level design methodologies
  • electrical and physical design, schematic capture, simulation/analysis, and layout and verification
  • frequency- and time-domain simulation and analysis
  • links from design to test
  • integrated waveform display & analysis capabilities supporting complex RF measurements
  • support for different types of simulation
  • system simulation with Visual System Simulator (VSS) design suite
  • time-domain simulation with Synopsys' HSPICE
  • frequency-domain simulation with AWR's harmonic balance simulator
  • open platform for third-party tool integration
  • SPICE socket for third-party SPICE-based circuit simulators
  • EM socket for third-party EM simulators
  • powerful and easy-to-use physical design suite.

High frequency design
High-frequency design in traditional EDA systems can mean users must undergo multiple design setup steps to obtain a particular analysis result from a selected simulator, resulting in the generation of many data files. In the Analog Office product, users set up multiple test benches and analysis measurements ahead of time (similar to a specification sheet) and then set up the parameters for the designs. As soon as the simulation is started, the system automatically: selects the 'right' simulator for the particular analysis, extracts the 'right' models for the design elements, runs the simulator(s), obtains the results and processes them into requested measurements, and presents the results in multiple graphs and tables.

The package also offers an interactive custom layout tool with integrated device-level, auto-placement, and auto-routing features to speed the creation of analog and RF circuit blocks and chips. An integrated DRC ensures that the physical layout being created always meets the process design rules, resulting in a correct-by-design, error-free layout.

To ensure proper modeling of inductance coupling between nets in gigahertz physical layout, the design system also integrates the interconnect extraction technology from OEA International's NET-AN 3D critical multi-net field simulator.

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