Scaling analog circuits and data converters in CMOS has always been a daunting task for designers. But those hurdles get taller as developers begin migrating toward design rules of 0.25 µm and below for lowering power consumption, size, and the cost of these complex chips. Subsequently, achieving the dynamic range, speed, bandwidth, and noise performance at sub-2-V operation poses many design challenges, as researchers push technology to its limits. Several ISSCC papers on this front reveal techniques to accomplish new goals at lower supply voltages by using advanced deep-submicron CMOS processes.
For the first time, Nyquist analog-to-digital converters (ADCs) have broken past speed records to sample above 1 Gsample/s. Oversampling ADCs also have pushed the low-power benchmark for GSM/EDGE digitizers down to 5 mW, while the search for a universal ADC has resulted in an adaptable architecture that covers 6 to 15 bits of resolution with bandwidths from 1 Hz to 10 MHz. Furthermore, the higher speed mania is pushing voltage-controlled oscillators (VCOs) toward the 50-GHz mark. The reported CMOS VCO topology operates both at high frequency and with a low voltage.
To serve leading-edge disk-drive read channels and high-speed Ethernet applications, researchers at UCLA's Electrical Engineering Department have developed a 6-bit CMOS ADC that exploits array averaging in a flash architecture to sample at 1.3 Gsamples/s (paper 8.1). The averaging technique reduces the effect of offsets, allowing the use of small transistors, and it provides higher speeds. This scheme implements averaging in both preamplifier stages and comparators to lower the input-referred offset from 8.1 to 2.8 mV (Fig. 1).
The ADC has a high-speed ROM-based encoder to convert thermometer code at the output of the latch array to quasi-Gray code, and then to binary code. A wideband track-and-hold amplifier precedes the flash quantizer to achieve better than a 5.5 effective number of bits (ENOB) for input frequencies of up to 600 MHz at a sampling rate of 1 Gsample/s. For 650-MHz inputs and 5 effective bits, the ADC can sample at 1.3 Gsamples/s.
The ADC consumes 500 mW at 3.3 V and a 1-GHz conversion rate (not including the output buffers). Power consumption goes to 545 mW as the conversion frequency is increased to 1.3 Gsamples/s. Integral and differential nonlinearity (INL and DNL) is below ±0.3 LSB at a 1-Gsample/s conversion. The dynamic performance at this rate is around 35 dB at a Nyquist input frequency of 500 MHz. The device occupies 0.8 mm2 of the active area in a 0.35-µm four-metal CMOS process.
Researchers at Philips Semiconductors have additionally achieved similar performance for a 6-bit flash CMOS ADC, but they use less silicon and power (paper 8.2). The company demonstrated a maximum sample rate of 1.1 Gsamples/s by combining interpolation and averaging techniques, along with a distributed sample-and-hold circuit.
This converter is a straightforward 6-bit full-flash ADC that consists of a resistive ladder with 63 taps followed by 63 comparators. The output from the comparator array feeds an encoder that converts thermometer code into 6-bit binary code. Unlike the UCLA approach, Philips' researchers used a distributed sample-and-hold stage, consisting of 15 differential circuits to simplify the design. According to the paper, each sample-and-hold circuit must be linear for only a small signal range as opposed to being linear over the entire input bandwidth. Implemented in 0.35-µm CMOS, the ADC occupies only 0.35 mm2 of silicon and consumes 300 mW at 3.3 V and a 900-Msample/s conversion rate. At this conversion rate, ENOB is 5 bits up to a 450-MHz input.
Other highlights of Session 8 included a 100-MHz pipelined ADC that dissipates only 180 mW from 1.8 V, and a 14-bit multistage pipelined 75-Msample/s ADC with a spurious-free dynamic range (SFDR) of 85 dB at the Nyquist input frequency.
In paper 8.3, designers from Texas Instruments Inc., Dallas, address sub-2-V issues for fast 10-bit pipelined CMOS ADCs. Here, the 100-MHz 10-bit ADC employs 0.5 bits of redundancy per stage to allow large offsets. In addition, to achieve high open-loop gain for each residue amplifier, it uses a two-stage op amp with Miller compensation. In short, it employs a traditional 9-stage architecture, with each stage resolving 1.5 bits. A sample-and-hold circuit is added upfront for better dynamic linearity for high-frequency input signals. To generate the final digital code, the 10-bit ADC uses digital error-correction circuitry (Fig. 2).
The device was fabricated in a 0.18-µm single-polysilicon standard digital CMOS process. At 1.8 V and 180 mW of maximum power consumption, it sets a new benchmark for any 10-bit 100-Msample/s CMOS ADC. The IC has 9.4 ENOBs for a 50-MHz input at the full sampling rate.
Using a 4-bit flash and a 4-bit residue stage, followed by eight 1.5-bit pipeline stages and a 3-bit flash, a 14-bit 0.35-µm polysilicon triple-metal CMOS ADC from Analog Devices Inc., Wilmington, Mass., flaunts 85 dB of SFDR without calibration or trimming, and an unprecendented conversion speed of 75 Msamples/s at 14 bits of resolution (paper 8.5). While the ADC uses digital correction to compensate for comparator errors, the 4-bit residue stage improves linearity and cuts power consumption in subsequent stages.
Because the capacitor size in this switched-capacitor pipeline design is determined by the noise and matching requirements, stage-1's input capacitor was kept to no more than 4 pF to meet the 70-dB noise budget. Together with 4-bit segmentation and careful layout, this capacitor sizing provides 14-bit DNL performance. The ADC's 2.7-V minimum supply mandates a small full-scale input range of 2 V p-p. Power consumption, including the core and output drivers, is 340 mW at 3 V.
Oversampling ADCs To accommodate drastically different symbol rates, signal bandwidth, and signal-to-noise ratio (SNR) requirements between the myriad of cellular-telephony specifications like wideband CDMA (WCDMA) and GSM, multistandard delta-sigma (Δ-Σ) ADCs have emerged with a wide dynamic range. These fast oversampling ADCs are making dual-mode telephony feasible. Toward that goal, Swiss researchers from the Integrated Systems Laboratory of the Swiss Federal Institute of Technology crafted a third-order feed-forward Δ-Σ ADC with the ability to digitize IFs for both WCDMA and GSM receivers (paper 3.1).To keep tabs on power consumption, this design places the IF at 3/4 of the sampling frequency instead of the common 1/4. Therefore, the sampling rates are 184.32 MHz for the WCDMA mode, and 104 MHz for the GSM channel. Built in 0.25-µm CMOS, the ADC consumes 13.5 mW at 185 Msamples/s, while power usage for the GSM band is only 11.5 mW. The dynamic range is 53 dB for WCDMA and 84 dB for GSM.
By employing a cascaded fourth-order Δ-Σ modulator, Motorola's French designers in Toulouse pushed the low-power benchmark for GSM/EDGE digitizers down to 5 mW, while maintaining 13.5 ENOB with a dynamic range of 84 dB (paper 3.2). The 0.35-µm CMOS modulator uses a 13-MHz clock to achieve such a wide dynamic performance over a bandwidth of 180 kHz.
Because power consumption is directly related to total circuit capacitance, an accurate estimation of thermal noise was made to determine the value of sampling and feedback capacitors in the first integrator. Then, the capacitors in the following stages were properly scaled to minimize overall power consumption. Significant portions of this digitizer operate from 1.8 V.
While papers 3.3 and 3.4 explore new approaches to dynamic element matching (DEM), the final two presentations in this session shed light on novel ADC architectures. To address element-mismatch issues inherent in multibit Δ-Σ architectures, researchers at Stanford University's Center for Integrated Systems in California developed a new DEM technique called partitioned data weighted averaging (P-DWA). This algorithm is implemented in the first 5-bit quantizer of a three-stage topology, followed by 3-bit second and third quantizer stages (paper 3.4).
Here, the traditional quantizer is partitioned into two sub-DACs, and DWA is performed independently on each sub-DAC. Simulations indicate that P-DWA eliminates the signal-dependent tone problem associated with conventional DWA at the cost of only a slight reduction in the peak SNR.
Furthermore, it cuts implementation complexity of an N-bit quantizer to that of two (N 1) quantizers. The quantizer's resolution is 15 bits at a conversion rate of 4 Msamples/s and a 95-dB dynamic range. Peak SNR is 90 dB. Implemented in 0.5-µm CMOS, the Δ-Σ modulator dissipates only 150 mW at 2.5 V, 90 mW of which is dissipated in the analog circuitry.
In search of the universal ADC, designers from Massachusetts Institute of Technology (MIT), Cambridge, proposed a reconfigurable architecture that can quickly adapt to pipelined or Δ-Σ topologies as well as adjust bias currents and circuit parameters to provide varying bandwidths and resolutions (paper 3.6). The basic building blocks of both pipeline and Δ-Σ topologies—op amps, comparators, switches, and capacitors—are integrated with a configurable switch matrix. In addition to one op amp, a switch matrix, and a decision circuit, each basic building block uses block-reconfiguration logic to control the switches' static connection and clocking. With a user-defined configuration word, the main reconfiguration logic determines the ADC's global structure and the state of each block (Fig. 3a).
The ADC is reconfigured at three levels. These include architecture (pipeline or Δ-Σ), resolution, and bandwidth. It offers a Δ-Σ mode for resolutions that are greater than 12 bits, and a pipeline mode for lower resolutions. For varying bandwidths, a PLL senses the clock frequency and varies the op amps' bias current automatically.
A methodology was created for interconnecting various blocks to reconfigure the adaptable ADC's resolution (Fig. 3b). For instance, a 12-bit pipeline mode employs blocks B1 to B6, while an 11-bit version uses blocks B2 through B7. A 10-bit model taps B3 to B7 blocks, and so on. An unused block is switched off to minimize noise and power. Likewise, a Δ-Σ mode uses a fourth-order cascade of integrators with distributed feedback and is embedded in blocks B1 through B4, with each block corresponding to a single integrator.
The ADC was fabricated in 0.6-µm double-polysilicon triple metal CMOS and occupies a total die area of 10.5 by 7.6 mm. By comparison, the reconfigurable ADC is slightly larger than a traditional 12-bit ADC. MIT's researchers argue that the prototype chip was optimized for testability and not area. Also, the measured INL and DNL exceed ±1 LSB due to a mismatch between the small capacitors used. The scientists say that this problem can be corrected by simply using standard digital calibration techniques.
Another paper (23.5) described a DAC advance, reporting the highest speed for a 12-bit CMOS DAC. Using extensive averaging and proper placement of current sources in a segmented current-steering architecture, developers at Katholieke University, Leuven, Belgium, demonstrated a 500-Msample/s DAC with an SFDR of 62 dB for a sinusoidal output signal of 125 MHz. The INL error is better than 0.3 LSB, further guaranteeing 12-bit accuracy. At this rate, the DAC consumes only 110 mW for a Nyquist output signal at 3 V.
As RF CMOS technology progresses into deep-submicron design rules, researchers are looking into building high-bit-rate broadband communication transceivers on a single chip using low-cost technology. That means that microwave and millimeter-wave VCOs must be first built in CMOS to get there. With that goal in mind, Bell Labs scientists in Murray Hill, N.J., realized an LC-resonator-based VCO in 0.25-µm CMOS for operation at 50 GHz (Fig. 4).
Bell's scientists say the fully integrated unit consumes less power than its counterpart in exotic compound semiconductor technologies, while providing comparable phase-noise and tuning performance (paper 23.8). Tests show that the bias condition for the VCO is set at 10 mA from a 1.3-V supply. Measured single-sideband phase noise is 99 dBc/Hz at a 1-MHz offset from the carrier. The tuning range is around 1.1 GHz with a 2.6-V variation in tuning voltage.
The VCO incorporates on-chip spiral inductors that are optimized using electromagnetic simulators for operation at 50 GHz. As a result, the LC resonator offers a quality-factor (Q) of about 10, which leads to lower power consumption and smaller parasitic capacitance. So, impedance matching appears to be a lesser issue in this approach.
New breakthroughs in CMOS imaging also were disclosed this year at the conference. A CMOS image sensor designed at Stanford University has crossed the 1-Gpixel/s barrier using a standard 0.18-µm CMOS (paper 6.1). With an ADC per pixel, this massively parallel digital pixel sensor can continuously output 10,000 frames/s at 8 bits/pixel to achieve a new milestone in image acquisition speed. This 352- by 288-pixel sensor uses 37 transistors for each of its 9.4- by 9.4-µm pixels.
Image sensors are incorporating more and more signal-processing functions on-chip, transforming themselves into image processors. Researchers at NEC Corp., Kanagawa, Japan, signal this trend with the design of a high-density CMOS image sensor that implements three additional signal-processing function modes: wide dynamic range, motion detection, and an edge-extraction mode (paper 6.6). Small pixel size and real-time operation are achieved by a four-transistor-pixel scheme and column-parallel on-chip analog operation.
These enhancements indicate that image sensors are relentlessly pursuing the silicon feature-size reduction path for low-cost system-on-a-chip (SoC) solutions. This will allow them to serve highly competitive consumer markets.