CT Delta-Sigma Experience

April 12, 2007
News on the business front includes National Semiconductor’s acquisition of Xignal. A year and a half ago, this German startup used its experience with serializer/deserializer (SERDES) IP for a breakthrough in bringing continuous-time delta-sigma to

News on the business front includes National Semiconductor’s acquisition of Xignal. A year and a half ago, this German startup used its experience with serializer/deserializer (SERDES) IP for a breakthrough in bringing continuous-time delta-sigma to market (see “‘Sample Wars’ And Silicon Technologies Energize ADCs”).

Xignal’s initial product used a third-order, continuous-time, delta-sigma modulator with a 4-bit quantizer stage that oversamples by a factor of 16. The internal sample clock operated at 640 MHz. Its self-adaptive, tunable loop filter supports sample rates from 20 to 40 Msamples/s. The fully differential input-signal path features a 30-MHz bandwidth.

Future family members will offer resolutions ranging from 12 to 18 bits and sample rates of hundreds of megahertz. Up to 80-Msample/s rates (at 14 bits) are anticipated, with an oversampling clock rate of approximately 1.3 GHz.

This January, National Semiconductor announced that it was acquiring Xignal, noting that Xignal’s “continuous time architecture greatly simplifies system design. That’s because it’s able to incorporate other signal path functions, such as on-board clocks, low-noise amplifiers, and external filters.

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