Electronic Design

D-Type Flip-Flop Synchronizes Multiplexer Data

Multiplexers are widely used in communication systems to convert parallel signals into serial signals. The multiplexer takes a high-frequency clock as the system input clock (Clk_in) that's synchronized with the serial output data. A low-frequency clock is derived from the Clk_in by the internal clock circuitry as an output clock (Clk_out) that can be used to trigger the parallel data input. Therefore, the parallel data input is well synchronized with the multiplexer as long as the data source is very close to it.

But in some applications, the multiplexer will probably be a bit far from the data source (e.g., they're on different pc boards). This causes a tough synchronization problem.

Let's take an example of an 8:1 multiplexer. Suppose the frequency of the input clock, Clk_in, is 1.25 GHz. Then the output clock, Clk_out, will be 155 MHz, only one-eighth of the input clock. The Clk_out that triggers the input data will be routed to a data-source board as the system clock by a coaxial cable (Fig. 1).

In this case, the coaxial cable length is 50 cm, and the length of the parallel datapath is around 40 cm. According to a formula derived by experience, the signal delay will be 5 ns per meter. This means the input-data delay is 4.5 ns. Because the period of the 1.25-GHz input clock is only 800 ps, the 4.5-ns delay can hardly be handled. How can one solve this problem?

Usually, Clk_in and Clk_out are well synchronized inside the chip. In other words, the clock edges are well aligned. So the problem becomes how to synchronize Clk_out with data_in. This is much easier because the period of Clk_out is eight times longer than Clk_in's, around 6.4 ns. The trick is to put a D-type flip-flop on the input data path, as shown in Figure 2. Now the problem is solved.

In this case, the MC100EP29DT from ON Semiconductor synchronizes the parallel input data. The clock trace from Clk_out to the MC100EP29DT should be kept as short as possible to eliminate delay. No matter how long it's delayed by the cables or traces, the input data will be ready at the rising edge of Clk_in. That's because the MC100EP29DT samples the data on the rising edge of Clk_out.

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