One significant development in the world of analog-to-digital converters (ADCs) has nothing to do with how they're built and everything to do with how they're supported. Companies now recognize that the entire conversion signal chain—front end, clock, and data converter—must work together. So, they're providing comprehensive tools that help ensure a successful design.
Some of these tools are Web-based, like National's Webench and Analog Devices' simADC and simCLK. Others are hardware-based, like Texas Instruments' TSW1100. This tool works with ADC hardware-evaluation boards to provide instant datacapture, processing, and graphics on a design engineer's desktop computer.
The delta-sigma architecture remains ideal for ADCs in pressure, flow-rate, and temperature transducers and weighscales—"near dc" performance at around 100 samples/s and up to 24 bits of precision. But delta-sigmas are pushing for broader and broader bandwidth, challenging pipelines.
That said, some data-converter experts opine that as deeper submicron technologies come to predominate, there also will be a resurgence of flash and flash/folding architectures relative to pipelines. That's because the power penalty for having many converters diminishes. There's still a problem with matching that will require calibration, but designers can deal with that.
Another architectural alternative is parallel/interleaved SARs. (Call it a gatling-gun approach, where a 1-Gsample/s converter might be built from 10 interleaved 1-Msample/s converters.) A challenge exists there, too, because the channel-to-channel mismatch must be digitally compensated. That type of design has been a staple of technical conferences for a few years, but some ADC gurus expect it to become more mainstream over the next several years.
In many cases, basic converter performance still determines the performance of the whole system, whether it's a cell phone, a TV, or a medical product. Yet more than half the R&D spent on converter development goes toward improving efficiency in various ways, from power consumption to integration level.
For example, discrete 12-bit, 60-Msample/s converters have been available for six or seven years. But in the latest OEM products, that functionality must be embedded—inexpensively and using less power, of course—in a wireless local-area network (LAN) chip set. So the technology is advancing, but within the framework of increasing integration in an existing performance frontier.
Jitter is the final frontier in ADC design. No matter how much you optimize the rest of your potential noise sources, clock jitter remains the ultimate barrier to performance. Interestingly, to minimize jitter noise, today's high-speed converter teams are working closely with their company's high-speed serial-IO teams, which generally have their own significant depth of experience in jitter control.
Generally, today's designers attack jitter in two ways: through high-Q tuned circuits or with broadband circuit with high gain-bandwidth products. In addition, chip designers must pay as much attention to the path from the clock input pin to the sample and hold (S/H) as they do to the path from the signal-input pin to the S/H.
Beyond architecture and jitter, a good sense of what's going on in the world of ADCs comes from a look at the implications of some applications.
In the medical field, digital imaging and storage are finally replacing film for x-rays. Dynamic range means the difference between seeing a mere shadow on the image and positively identifying a tumor. The magic number? 22 bits. This performance is now commonly available at low price points.
In digital photography, each new camera generation sees an increase in pixel count. Recently, though, performance requirements have stabilized. So, camera OEMs have been asking chip makers to focus on integration in smaller geometries to lower camera street cost and extend battery life.
For more, see "ADCs At ISSCC" at www. elecdesign.com, Drill Deeper 11839.