The three most popular ADC types generally found in analog front ends are successive-approximation (a), pipelined (b), and delta-sigma (c). These block diagrams represent extremely simplified concepts of the architectures.
a. In successive-approximation ADCs, an analog input voltage is "freeze-framed" by a sample-and-hold. Then, an N-bit register is set to mid-scale: The most significant bit of the register is set to 1, forcing the DAC output to its mid-range value. If the input voltage is greater than the DAC output, the comparator output is true and the MSB remains at 1. But if the input voltage is below the DAC output, the MSB of the register is cleared to logic 0. The converter control logic then moves to the next bit down, forces that bit high, and performs another comparison, all the way down to the LSB. When the conversion is complete, the N-bit digital word is available in the register. See Associated Figure
b. In pipelined ADCs, each parallel stage works on one or more bits of successive samples concurrently. The analog input is applied to a sample-and-hold, and the stage-one ADC quantizes it to 3 bits. This is then fed to a small DAC, and the analog output is subtracted from the value output from the sample-and-hold. This "residue" is amplified and fed to the next stage, and so on. Shift registers align the bits from each stage in time and pass the combined sample on to error-correction logic.See Associated Figure
c. Delta-sigma converters don't easily yield to a straightforward analysis in the time domain, and they are better understood in the frequency domain. (Intersil Applications Note 9504 at www.intersil.com/data/an/an9504.pdf provides a detailed mathematical analysis.) Suffice it to say that grossly oversampling the input signal (sampling it far above the Nyquist value for the top of the input frequency band of interest) precludes aliasing. On top of that, it spreads the frequency components of quantization noise (the resolution errors caused by digitizing the continuous input signal into a series of discrete levels) over a wider bandwidth. This reduces the average level of the quantization noise and shifts most of it up in frequency. Most of the noise can then be removed by digital filter with a sharp cutoff above the band of interest.See Associated Figure
