Electronic Design
Dissecting The High-Speed Amplifier/AAF/ADC Interface

Dissecting The High-Speed Amplifier/AAF/ADC Interface

robReeder-HWhen using an active front-end amplifier to drive a high-speed converter, designing an anti-aliasing filter (AAF) can be a difficult task. It’s important to get it right because anti-aliasing is the characteristic that prevents unwanted noise outside the band of interest from falling in-band. Understanding the need for a good AAF is key to any successful high-speed analog signal chain design, yet the devil is in the details when it comes to designing an AAF that performs as required.

IF Sampling And Nyquist Considerations

IF sampling allows the designer to eliminate a mix-down stage in the signal chain. This gives rise to better performance because the number of overall components in the signal chain is reduced, lessening the noise to the system. This in turn better preserves the system’s overall signal-to-noise ratio (SNR). In certain situations it can also improve the spurious-free dynamic range performance (SFDR), because the elimination of this stage reduces the local oscillator (LO) leakage through the mixer.

Baseband sampling may be appropriate when the signal or frequency of interest lies within the first Nyquist zone. However, some converters can sample in higher Nyquist zones above the first. This is called undersampling or IF sampling. In Figure 1, the signal is in the forth Nyquist zone. Its image or alias can be seen reflected back to the first Nyquist zone, where it looks like a 20-MHz signal.


1. Undersampling (or IF sampling) occurs when a converter samples in Nyquist zones higher than twice their sampling frequency (FS). For example, if the ADC sampling frequency were 80 MHz and the frequency of interest were 140 MHz, it would be in the forth Nyquist zone.

Most fast Fourier transform (FFT) analyzers such as Visual Analog1 only plot an FFT of the first Nyquist zone (0 FS to 0.5 FS). Therefore, if the frequency of interest is above 0.5 FS, an image is reflected down to the first Nyquist zone or what is also known as baseband. This can make things confusing if spurious tones are in the band of interest.

According to Walt Kester’s High Speed Design Seminar,2 an analog-to-digital converter (ADC) can sample above 0.5 FS and still hold true to the Nyquist criteria. The signal must be sampled at a rate equal to or greater than twice its bandwidth to preserve all of its information. This is also seen in:

FS > 2 × FBW        

where FS is the sample frequency and FBW is the maximum frequency of interest. The key here is the location of the frequencies of interest. As long as the signals do not overlap and stay within a single Nyquist zone, the Nyquist criteria is met. The only thing that changed is the location of the first Nyquist zone to a higher one.

Starting The AAF Design

An AAF helps to reduce signal content from unwanted Nyquist zones that would otherwise alias in-band and corrupt dynamic performance of the signal chain. AAFs are often designed using LC networks and need to have well-defined source and load impedances to achieve the desired stop-band and passband characteristics. To derive the filter network, a variety of cookbook filter synthesis approaches may be used. Often, Chebyshev or Butterworth polynomials are used to define the filter transfer function.

Deciding between a Chebyshev or Butterworth filter, or any other filter type for that matter, depends entirely on the requirements of the filter’s application. The Butterworth filter exhibits a generally well-rounded response with maximal passband flatness (0 dB of ripple) and good phase response. On the other hand, a Chebyshev filter of the same order sacrifices maximal passband flatness (i.e., ripple increases) and phase response to achieve a greater stopband attenuation, or roll-off.13

Several software-based filter design programs are available to help simplify the problem, such as Filter Free 4.0 from Nuhertz Technologies,4 the Quite Universal Circuit Simulator (QUCS),5 or Agilent Technologies’ Advanced Design System (ADS).6 As a first step, start with this general approach to the design of the amplifier/ADC interface assuming a bandpass filter is used to achieve optimum performance (bandwidth, SNR, and SFDR):

  • The amplifier should see the correct dc load recommended by the datasheet for optimum performance.
  • The correct amount of series resistance must be used between the amplifier and the load presented by the filter to prevent undesired peaking in the passband.
  • External parallel resistors should reduce the input to the ADC, and the correct series resistance should be used to isolate the ADC from the filter. These series resistors also reduce peaking in the passband.

An AAF design approach that takes advantage of the relatively high input impedance of most high-speed ADCs and the relatively low impedance of the driving source (amplifier) can be understood by reference to a generalized circuit (Fig. 2). The core of the design process consists of seven steps:

  • Set the external ADC termination resistors, RTADC, so the parallel combination of RTADC and RADC is between 200 Ω and 400 Ω.
     
  • Select RKB based on experience and/or the ADC datasheet recommendations, typically between 5 Ω and 36 Ω.
     
  • Calculate the filter load impedance using:

    ZAAFL = 2RTADC || (RADC + 2RKB)
     
  • Select the amplifier external series resistor RA. Make RA less than 10 Ω if the amplifier differential output impedance is 100 Ω to 200 Ω. Make RA between 5 Ω and 36 Ω if the output impedance of the amplifier is 12 Ω or less.
     
  • Select ZAAFL so the total load seen by the amplifier, ZAL, is optimum for the particular differential amplifier chosen using:

    ZAL = 2RA + ZAAFL
     
  • Calculate the filter source resistance:

    ZAAFS = ZO + 2RA
     
  • Using a filter design program or tables, design the filter using the same source and load impedances, ZAAFS and ZAAFL. This helps to reduce the amount of loss in the filter. Any mismatch between the input/output impedance has a loss of 10*log(input Z/output Z). For example, with an input impedance of 50 Ω and an output impedance of 200 Ω, the loss of the filter is –6.0 dB or 10*log(50/200). Also, use a bandwidth that is about 10% higher than the desired bandwidth of the application passband to ensure flatness in the frequency span.


2. This generalized circuit is similar to most high-speed differential amplifier/ADC interfaces. It will be used to explain how to minimize filter insertion loss by taking advantage of the relatively high input impedance of most high-speed ADCs and the relatively low impedance of the driving source.

After running these preliminary calculations, the circuit should be quickly reviewed for the following specifications:

  • The value of CAAF3 should be at least 10 pF so it is several times larger than CADC. This minimizes the sensitivity of the filter to variations in CADC.
     
  • The ratio of ZAAFL to ZAAFS should not be more than about 7 so the filter is within the limits of most filter tables and design programs. Ideally, they should be the same to minimize loss.
     
  • The value of CAAF1 should be at least 5 pF to minimize sensitivity to parasitic capacitance and component variations.
     
  • The inductor, LAAF, should be a reasonable value of at least several nanohenries.
     
  • The value of CAFF2 and LAAF1 should be reasonable values. Note that circuit simulators sometimes can make these values too low or too high. To make these values more reasonable, simply ratio them with better standard value components that maintain the same resonant frequency (Fig. 3).


3. If the simulated values value of CAFF2 and LAAF1 are unreasonable, use standard-value L’s and C’s that produce the same resonant frequency while maintaining the ratio of component values provided by the simulator.

In some cases, the filter design program may provide more than one unique solution, especially with higher-order filters. The solution that uses the most reasonable set of component values should always be chosen. Also, choose a configuration that ends in a shunt capacitor so it can be combined with the ADC input capacitance.

AAF Tradeoffs

The parameters in this interface circuit are very interactive, so it’s almost impossible to optimize it for all key specifications (bandwidth, bandwidth flatness, SNR, SFDR, and gain). However, the peaking, which often occurs in the bandwidth response, can be minimized by varying RA and RKB.

Figure 4 shows how the passband peaking is reduced as the value of the output series resistance, RA, is increased. But as the value of this resistance increases, there’s more signal attenuation, and the amplifier must drive a larger signal to fill the ADC’s full-scale input range.


4. Increasing output series resistance, RA, reduces passband peaking. Unfortunately, at the same time, the signal is attenuated because the amplifier must drive a larger signal to fill the ADC’s full-scale input range.

The value of RA also affects SNR performance. Larger values, while reducing the bandwidth peaking, tend to slightly increase the SNR because of the reduction in bandwidth and unwanted noise.

Select the RKB series resistor on the ADC inputs to minimize distortion caused by any residual charge injection from the internal sampling capacitor within the ADC. Increasing this resistor also tends to reduce bandwidth peaking. But just as RA increases RKB, increasing signal attenuation, the amplifier must drive a larger signal to fill the ADC input range.

For optimizing center frequency passband characteristics, the series capacitor, CAAF2, can be varied by a small amount. The designer then can get the best optimal frequency coverage for the application.

Normally, the ADC input termination resistor, RTADC, is selected to make the net ADC input impedance between 200 Ω and 400 Ω, which is typical of most amplifier characteristic load values. Using too high or too low a value can have an adverse effect on the amplifier’s linearity.

Putting It All Together

By following these steps, it’s possible to arrive at a narrow bandpass receiver front end based on the ADL5565 ultra-low-noise differential amplifier driver and the AD9642 14-bit, 250-Msample/s ADC (Fig. 5).


5. The process described in the text yielded this narrow bandpass receiver front end based on a third-order Butterworth AAF. The 0.1-µF capacitors are used to block the common-mode voltages between the amplifier, its termination resistors, and the ADC inputs.

The third-order Butterworth AAF is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB. In this ac coupled design, the 0.1-µF capacitors are used to block the common-mode voltages between the amplifier, its termination resistors, and the ADC inputs.

The overall circuit has a bandwidth of 18 MHz with a passband flatness of 3 dB. The SNR and SFDR measured with a 127-MHz analog input are 71.7 dBFS and 92 dBc, respectively. The sampling frequency is 205 Msamples/s, positioning the IF input signal in the second Nyquist zone between 102.5 MHz and 205 MHz.

The circuit accepts a single-ended input and converts it to differential using a wide bandwidth (3 GHz) 1:2 transformer. The 6-GHz ADL5565 differential amplifier has a differential input impedance of 100 Ω when operating at a gain of 12 dB to compensate for the insertion loss of the filter network and transformer (approximately 5.8 dB), providing an overall signal gain of 5.5 dB.

An input signal of +1.5 dBm produces a full-scale 1.75-V p-p differential signal at the ADC input. The AAF is a third-order Butterworth filter designed with a standard filter design program. A Butterworth filter was chosen because of its passband flatness. A third-order filter yields an ac noise bandwidth ratio of 1.05.

To achieve the best performance, load the ADL5565 with a net differential load of 200 Ω. The 15-Ω series resistors isolate the filter capacitance from the amplifier output, and the 100-Ω resistors in parallel with the downstream impedance yield a net load impedance of 217 Ω when added to the 30-Ω series resistance.

The 5-Ω resistors in series with the ADC inputs isolate internal switching transients from the filter and the amplifier. The 2.85-kΩ input impedance was determined using the downloadable spreadsheet on the AD9642 Web page.7 Simply use the parallel track mode values at the center of the IF frequency of interest. The spreadsheet shows both the real and imaginary values.

The third-order Butterworth filter was designed with a source impedance (differential) of 200 Ω, a load impedance (differential) of 200 Ω to minimize the filter loss, a center frequency of 127 MHz, and a 3-dB bandwidth of 20 MHz. Figure 3 shows the calculated values from a standard filter design program. Because of the high values of series inductance required, the 1.59-µH inductors were decreased to 620 nH, and the 0.987-pF capacitors increased proportionally to 2.53 pF, maintaining the same resonant frequency of 127 MHz, with more realistic component values.

The internal 2.5-pF capacitance of the ADC was subtracted from the value of the second shunt capacitor to yield a value of 37.3 pF. In the circuit, this capacitor was located near the ADC to reduce/absorb the charge kickback.

Figure 5 shows the values chosen for the final filter passive components after adjusting for actual circuit parasitics. The table summarizes the measured performance of the system, where the 3-dB bandwidth is 18 MHz, centered at 127 MHz. The total insertion loss of the network is approximately 5.8 dB. Figure 6 plots frequency response and SNR/SFDR.


6. Plotted curves show passband flatness performance versus frequency (a) and SNR/SFDR performance versus frequency (b). Both represent a sample rate of 205 Msamples/s.

Further Observations

Understanding all the different factors, parameters, and tradeoffs that can be involved in designing an AAF in between an amplifier and ADC can be more difficult than it seems. In the above design, each parameter was given equal weight. Therefore, the values chosen are representative of the interface performance for all the design characteristics. In some designs, different values may be chosen to optimize SFDR, SNR, or input drive level, depending on system requirements.

Acknowledgements

The author would like to acknowledge David Brown and Ankit Gupta for their help in the lab and collecting all the measurement data.

References

  1. Design Tools: ADIsimADC
  2. High Speed Design Seminar, Walt Kester, ISBN 0916550079, 9780916550073
  3. AN-827, “A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs,” Rob Reeder and Eric Newman
  4. Nuhertz Technologies, Filter Free Filter Design Program.
  5. Quite Universal Circuit Simulator
  6. Advanced Design System (ADS), Agilent Technologies.
  7. AD9642: 14-bit, 170-MSPS/210 MSPS, 1.8-V analog-to-digital converter (ADC).
  8. Reeder, Rob, “Achieve CM Convergence Between Amps And ADCs,” Electronic Design, July 2010
  9. Reeder, Rob, Michael Elliott, “Kicking Back At High-Speed, Unbuffered ADCs,” Electronic Design, July 2011
  10. CN-0227: High Performance, 16-Bit, 250 MSPS Wideband Receiver with Antialiasing Filter
  11. CN-0279: High IF Sampling Receiver Front End with Bandpass Filter
  12. Bowick, Chris, RF Circuit Design, Newnes, February 1997
  13. ADL5565: 6 GHz Ultrahigh Dynamic Range Differential Amplifier.

 

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