Electronic Design

Dueling 12-Bit ADCs Make Their Debut

The highest demand and the most vigorous competition between companies that make analog-todigital converters (ADCs) lie in the sampling range from 50 to 65 Msamples/s in 10- and 12-bit resolutions. Market demand is highest for eight- and 10-channel devices with the lowest possible power consumption per channel.

In late January, within days of each other, Texas Instruments and National Semiconductor announced groundbreaking new chips for that market segment. In terms of wow-factor, National took some of the wind out of TI’s sails by developing its chip in an entirely new architecture for commercial applications: continuous-time delta-sigma.

Partly due to the new architecture, there was a dramatic development. Where TI had announced chips that use 30% less power than their closest competitor (of the week before), National’s chips use 30% less power again.

TI’s 12-bit ADS5281 (50 Msamples/s), 12-bit ADS5282 (65 Msamples/s), and 10-bit ADS5287 (65 Msamples/s) cost $60.00, $68.40, and $40.00 in lots of 100, but only the ADS5281 was available for sampling as of late January. Sampling now, National’s 12-bit, 50-Msample/s ADC12EU050 costs $64.00 in 1000-unit quantities.

HEAD TO HEAD
TI’s chips offer scalable power dissipation that ranges from 48 mW/channel at 30 Msamples/s to 55 mW at 40 Msamples/s; 64 mW at 50 Msamples/s; and 77 mW at 65 Msamples/s (see the figure). Their signal-to-noise ratio (SNR) is 70 dBFS at a 10-MHz intermediate frequency (IF). They come in a 9- by 9-mm, 64-pin quad flat nolead (QFN) package.

According to National Semiconductor, the ADC12EU050 offers a typical per-channel power consumption of 40 mW at 40 Msamples/s and 44 mW at 50 Msamples/s. Its SNR is 70 dBFS at a 3.5-MHz IF. The chip comes in a 68-pin, 10- by 10-mm leadless leadframe package (LLP).

Special features in the TI chips accommodate the different needs of the applications they target. A low-frequency noise-suppression mode eliminates 1/f (flicker) noise, improving SNR by up to 4.2 dB over a 1-MHz band in baseband and time-domain applications. Particularly in ultrasound applications, where an implanted bit of metal in a body can provide a much stronger echo than bone or soft tissue, overload-recovery circuitry allows each of TI’s ADCs to provide valid data within one clock cycle after an input overload as high as 6 dB. At the other end of the signal-strength spectrum, 0- to 12-dB programmable gain boosts input signals as low as 0.5 V p-p to improve dynamic range. TI’s chips also have a companion eight-channel amplifier, the VCA8500, expressly for medical-imaging applications.

Some of the National ADC12EU050’s special features take advantage of the oversampling architecture. Thanks to its integrated low-pass, brick-wall anti-aliasing filter, no external anti-aliasing filter is necessary. The continuoustime architecture also means the IC has an easy-to-drive, purely resistive input stage that, of course, does not require a sample-and-hold amplifier.

National has overcome the continuous-time architecture’s traditional susceptibility to clock jitter with an integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO) for clock conditioning. Like the TI converters, the National devices provide on-chip instant-overload recovery circuitry that recovers from saturation within one clock cycle if the input exceeds pre-determined limits.

In both cases, these parts are just beginning to sample. Datasheets are still only a few pages long. Additionally, most characteristics are “typical.” (The Texas Instruments datasheet does include some guaranteed minimums.) Any design team working on a project that might use one or the other will likely be in touch with both companies and their application-support engineers.

WHENCE CONTINUOUS TIME?
Check out “A Continuous-Time S-? Modulator with 88dB Dynamic Range and 1.1MHz Signal Bandwidth” by Shouli Yan of the University of Texas and Edgar Sánchez-Sinencio of Texas A&M. Presented at the 2003 International Solid State Circuits Conference, it’s available at http://users.ece.utexas.edu/~slyan/data/yan_isscc03.pdf.

In a nutshell, a continuous-time converter moves the sampling operation from the input to the ADC to just after the forward loop filter in the delta-sigma modulator. (Analog Devices claims trademark rights to the term “Sigma-Delta.” Electronic Design uses the term “delta-sigma” in reference to non-ADI oversampling ADCs.)

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What’s so good about moving the sampling operation downstream? In a discrete-time delta-sigma ADC, there is, as in most ADCs, a switched-capacitor filter. Designing one requires the creation of fast settling circuits and an input buffer to eliminate sample glitches.

Also, switched-capacitor input filters set their poles and zeroes through capacitor ratios relative to the sampling clock frequency. Because capacitor thermal noise is inversely proportional to capacitance, the capacitors must be relatively large to obtain the best SNR.

In addition, to acquire an accurate representation of the input signal on a hold capacitor, the input stages must settle to a finite level dictated by the accuracy limits of the system. During acquisition, settling time depends on the systems’ exponential time constant and slew rate.

Why design discrete-time ADCs, then? Discrete-time input filter characteristics scale with clock frequency. Filter performance, therefore, always matches the sample clock rate. (One penalty for this, though, is that the higher the clock frequency, the more dynamic power is consumed.)

That link with the clock rate has made discrete-time attractive over the years. In a continuous-time design, the filter characteristic depends on conventional active-filter design rules. If the sample rate is changed to match input-signal bandwidth, the continuous-time filter must be retuned.

It becomes a real challenge to ensure that a wide range of sample rates can be supported from a single product platform. A further problem lies in achieving high linearity in highresolution implementations, because the loop filter requires a great deal of gain.

Continuous-time design was so difficult, it remained essentially a laboratory curiosity for decades. Yet in 2005, Xignal, a fabless German company with just 33 employees, said it could stabilize the clock using a novel inductive tank circuit.

Somewhat counterintuitively, Xignal also found that exploiting deep-submicron CMOS processes helped make highspeed delta-sigma modulators a reality. Not only do they help lower the cost of implementing complex multistage digital filters, they also support high clock rates, allowing wide inputsignal bandwidths. The rest of Xignal’s innovation included a high-speed, multibit third-order modulator and a tunable, high-gain, continuous-time loop filter stage.

In the long run, Xignal determined that the fabless model wasn’t going to be the route to riches in the world of ADCs. National acquired the company in January 2007 and put on a full-court press, applying its design and manufacturing prowess to productize Xignal’s innovation. The result was the ADC12EU050.

See Associated Chart

See Associate Figure

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