Electronic Design

Evaluating Timing IP

Sponsored by: TRUE CIRCUITS INC.

A phase-locked loop (PLL) is pretty basic. How much can one IP vendor's PLL differ from another's?

While the high-level PLL schematic is simple, the simplest PLLs don't perform well. They all accept a reference clock and generate another clock, frequency multiplied and/or phase-locked to the reference. Yet PLLs from different IP vendors offer different features, flexibility, and output quality. The right PLL can make the design of the clocking system easier and more robust by providing flexible clock multiplication capability and multiple phase-locked outputs at different frequencies or at different precise fractional phase offsets of the clock period. The wrong PLL can impede chip bring-up and production ramp by requiring lab work to discover process-dependent tweaking factors necessary to make the PLL operate as specified. There are differences in how closely vendors work with their licensees as well.

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