Electronic Design

Expand Your I/O With The I²C Bus

In system applications where various input signals are monitored or several output signals are controlled, these lines are sometimes connected directly to the microprocessor pins. Such monitoring and controlling is done in software. However, this technique may require many microprocessor pins.

To conserve microprocessor pins, one alternative is to have the monitored and controlled lines communicate with the microprocessor through a glue-logic interface. In this case, fewer lines are connected to the microprocessor pins. But in either scenario, developing such systems is more cumbersome and time-consuming because it requires more devices, the routing of more traces, or the development of code that's more complex.

Here's a good solution for monitoring and controlling several peripheral signals. It provides a simple cost-effective method of accessing a parallel bus and a convenient means of interfacing with different electronic devices. The technique is based on the industry-standard PCF8574 and PCF8574A devices. These products differ in their inter-integrated circuit (I2C) addresses. This article refers to both devices as the expander. When discussing differences, the specific device is called by name.

The expanders have a two-wire I2C communication bus that can interface with an I2C master for bidirectional data transfers. The I2C bus consists of two active wires and a ground connection. The active wires are a bidirectional serial data (SDA) line and a bidirectional serial clock (SCL) line (Fig. 1). Both SDA and SCL are joined to a positive supply voltage via a pull-up resistor. When the bus is idle, both lines are pulled high.

Depending on its functionality, every device linked to the I2C bus has its own unique address and can act as a receiver and/or transmitter. The expanders can be configured to have a unique 7-bit address. The first four bits of the PCF8574's 7-bit address are 0100, and those for the PCF8574A are 0111. The lower three bits are the settings on device pins A2, A1, and A0. Therefore, the complete unique address of a device is determined by the setting on the A2, A1, and A0 pins. The table shows the unique addresses of the PCF8574 and PCF8574A for the various possible settings.

The ability to set unique addresses for the devices makes it possible to have up to eight PCF8574 and eight PCF8574A devices on the same I2C bus. As each device has eight I/O pins, a single I2C bus can control as many as 128 I/Os if PCF8574 and PCF8574A are employed.

I2C communication with the expanders is initiated by the master, which sends the address bits of the slave device to be communicated with. The first part of the address byte consists of a 4-bit address code, which is set to 0100 for the PCF8574 device and 0111 for the PCF8574A device. Three chip-select bits (A2, A1, and A0) follow the address code. These enable the use of up to eight PCF8574 and eight PCF8574A devices on one bus and determine which device is accessed. For the device to respond, the chip-select bits in the address byte must correspond to the logic levels on the corresponding A2, A1, and A0 pins. Figure 2 shows an example circuit that uses up to eight PCF8574 and eight PCF8574A devices to control and monitor up to 128 I/Os.

For additional information on using PCF8574 and PCF8574A, see Texas Instruments' application report, Improving System Interrupt Management Using the PCF8574 and PCF8574A I/O Expanders for the I2C Bus, literature number SCPA032.

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