Hardware Algorithm Fine-Tunes Converters For Best Compression

Future analog-to-digital converters (ADCs) that implement Samplify Systems' latest algorithm could compress digitized, band-limited signals by adapting to the signals' bandwidth and dynamic range.

With it, designers would be able to stream compressed data at rates significantly below the converter's sampling rate, as well as store more compressed data in the same memory. Storage-scope users could manually trade off between capture duration and signal quality. Implementing the new compression algorithm in silicon adds only a few cents to the manufacturing cost of ADCs and digital-to-analog converters.

Next week, readers on the West Coast will be able to see Samplify Systems' technology for themselves in a hardware demonstration showing the algorithm implemented in an FPGA board. The demo will be accompanied by a paper delivered at the GSPx International Embedded Solutions Event in Santa Clara, Calif. Also, downloadable software will use real-life sampled data files to demonstrate how data rate can be traded off for distortion.

Samplify starts with a patented lossless compression engine for bandlimited signals. Lossless compression ratio is reduced as the occupied signal bandwidth increases, but 2:1 lossless compression is often possible. The center frequency of the signal of interest can be anywhere from dc to Nyquist. Examples of bandlimited signals include individual channels in a wireless system, signals from ultrasound, mechanical vibration, and radar sources.

For a 20% bandwidth-limited signal with a 75-dB signal-to-noise ratio (SNR), Samplify's algorithm yields roughly 2:1 lossless compression. The amount of compression can be further increased by analyzing the noise floor and headroom requirements of the signal and then applying noise reduction prior to compression.

For instance, if channel impairments reduce the original signal's 75-dB dynamic range to 50 dB, 2.88:1 lossy compression is possible. Using this example, a 100-Msample/s uncompressed sample stream is reduced to a 36-Msample/s compressed sample stream. When only simple signal characteristics such as dc level or jitter are of interest, capture duration could be increased still further, because very little dynamic range would be required.

Demos will take place at GSPx booth 424 (Nallatech) on Sept. 29. The Samplify paper will be presented the same day.