High performance 12 and 14bit ADCs break the 100mW power barrier

Munich, Germany: Billed as the industry’s lowest power 14 and 12bit, 40MHz analog-to-digital converters (ADCs), Xignal Technologies’ latest products are based on Continuous Time Delta Sigma (CTΔΣ) technology. The devices consume 70mW while operating at 20-40 MSPS data rate and this, says the company, is the first time such performance has been available at the sub-100mW power level.

These design of these ADCs eliminate anti-alias filters and simplify system design by providing an on-chip, precision (low jitter) sample clock. Additionally, the devices are easy to drive and do not require a differential input buffer. They can handle 4V peak-peak input signals while operating from a 1.2V DC supply and they offer good linearity and signal-to-noise (SNR) performance.

The XT11 family uses a fast, third-order continuous time delta sigma modulator combined with an on-chip digital filter and tuneable loop filter. The advantage of this is it cuts the design effort needed to deploy a high performance data acquisition system.

Despite offering a power Figure of Merit (FOM) half that of current pipeline ADCs, there is no trade-off in linearity or electrical performance. The XT11400 ADC has a signal-to-noise ratio (SNR) of 76 dB and total harmonic distortion (THD) of -82 dB while the XT11200 ADC turns in an SNR of 71 dB and THD of -78 dB.

Previous low-voltage ADCs have only been able to handle limited analog input signal ranges, typically less than the supply voltage. This works against achieving high SNR and low THD. Attempts to increase dynamic range have traditionally been at the expense of increased power consumption. In contrast, Xignal’s ADCs can handle 4V peak-peak signal levels - over three times their 1.2V operating voltage.

Accurate clock signals are key to an ADC achieving high dynamic range; errors in clock signals (e.g. jitter) show up as errors in the ADC conversion process, and consequently a reduction in the SNR of the device.

The XT11 family members use a proprietary self-clocking circuit that eliminates the need for an external complex clocking scheme. The on-chip clock is driven from an external crystal (ranging from 13.5 to 27 MHz). An on-chip inductive resonator based PLL generates a clean (low jitter) sample clock that is also brought to an external pin and made available for use as an accurate reference clock for other components on the printed circuit board. This is ideal for parallel operation of multiple ADCs in multi-channel systems.

Conventional pipeline ADC’s require sample-and-hold amplifiers comprising distributed switched capacitors as the input stage to the ADC quantiser. These capacitive stages require an external, fast and high bandwidth differential amplifier to drive the resulting complex impedance of the input stage. However, these products do not require sample and hold circuit to function. They use a simple, current driven (resistive) input stage. What this does is eliminate the need for external differential drivers thereby reducing overall system cost, design time and system power.

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