Electronic Design
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High-Speed ADC Input Impedance: A Measured Versus A Mathematical Approach

Designing with high-speed analog-to-digital converters (ADCs) often begs the question: “What does the analog input impedance of the ADC look like over frequency?” The datasheet only gives one point. If you’re dealing with intermediate frequencies (IFs) greater than 100 MHz, then what is the input impedance? Does it change at various frequencies or does it stay fixed?

When considering any new part in the signal chain, input/output impedance is usually an important spec to “bolt” the necessary signal-chain blocks together properly. For a high-speed converter, this specification has become a key issue because designs, particularly those in communications infrastructure, have moved IFs from 20-MHz baseband to over 200 MHz (4th Nyquist Zone if sampling at 122.88 MHz) and climbing.

In the old pre-Y2K days, impedance was generally “considered” high—several kW—at baseband, and still is. However, with increasing IF frequency designs, questions regarding the actual impedance and whether it moves over frequency will occasionally pop up. Typically, the datasheet specifies differential input impedance as a simple parallel RC combination. However, not every ADC spells out what this really means.

To Buffer Or Not To Buffer

When considering input impedance effects, designers can generally choose between two types of high-speed ADCs: buffered and unbuffered (i.e., switched capacitor). Though many different converter topology choices are out there, the applications here deal with pipeline architectures.

The popular CMOS switched-capacitor ADC doesn’t have an internal input buffer. Thus, its power dissipation is much lower than buffered types. The external front end connects directly to the ADC’s internal switched-capacitor sample-and-hold (SHA) circuit, which presents two problems.

First, the input impedance varies with frequency and mode as it switches between sample and hold. Second, the charge injection from the internal sampling capacitors and network reflects a small amount of signal, which is packed with high-frequency content (Fig. 1), back onto the front-end circuitry and incoming signal. This may cause settling errors for the elements (active or passive) connected to the analog inputs of the converter.

Fig 1. The plots reflect the internal sampling capacitors' time-domain charge injection (single-ended) versus frequency-domain charge injection.

In general, the input impedance of this type of converter is very high (in the several kW range) at lower frequencies (<100 MHz) and rolls off to roughly 200 Ω above 200 MHz differentially. The imaginary, or capacitive, part of the input impedance also starts out at a fairly high level and tapers off to about 1 to 2 pF at high frequencies. “Matching” this input structure is a rather challenging design problem, especially at frequencies greater than 100 MHz.      

The differential makeup of these inputs is important, especially for frequency-domain designs. A differential front-end design allows for better common-mode rejection of the charge injection, and it helps the design.

It’s easier to design with buffered-input converters. The tradeoff, though, is that this type of converter consumes more power because the buffer is designed to be very linear and have low noise. The input impedance is usually specified as a fixed, differential R||C impedance. This is buffered by a transistor stage that drives the conversion process at low impedance, so charge-injection spikes and switching transients are significantly reduced.

Unlike switched-capacitor ADCs, the input termination has little variation between the sample and hold phases of the conversion process. Thus, it’s much easier to design the proper “drive” circuit versus its unbuffered brother. Figure 2 shows a simplistic view of the internal sample-and-hold circuit for buffered and unbuffered ADCs.

Fig 2. Shown is a comparison of a sample-and-hold circuit for unbuffered (a) and buffered (b)high-speed pipeline ADCs.

Converter choices can be challenging, but most designs today strive for lower power. As a result, designers will opt for an unbuffered converter. If linearity performance is a higher priority over power consumption, then buffered converters are commonly used. Keep in mind that for either converter scenario, the higher the application frequency, the more challenging the front-end design. Simply choosing a buffered converter will not solve every issue. However, in some cases, it may reduce complexity.

Converter Input Impedance: Measurement Approach

On the surface it may seem daunting, but there are several ways to measure a converter’s impedance. The trick is to have a network analyzer do most of the legwork. This equipment may come with a considerable price tag, though. The advantage is that today’s network analyzers perform many more functions, like trace math and de-embedding, and then spit out a direct answer without using external software programs for tasks such as impedance conversion.

Measuring a converter’s impedance requires two boards, a network analyzer, and a little “hacking” knowledge. The first board, which has the ADC/DUT (device under test) installed, is populated so it can be biased and clocked (Fig. 3a). This high-speed ADC evaluation board has the front-end circuitry stripped away to expose only the traces to the converter’s analog input pins (Fig. 3b).

Fig 3. Impedance measurement for a converter requires an ADC evaluation board (a) with the front end stripped away and prepped for measurement (b)

The second board de-embeds any trace parasitics of the removed front-end circuitry. To do this, an exact copy of the board in Figure 3b must be used, though it should be unpopulated (Fig. 4a). This bare board is then cut down to the point where only those front-end circuitry traces go to the ADC’s analog input pins (Fig. 4b).

Fig 4. To de-embed trace parasitics of the removed front-end circuitry an unpopulated version of the board in Figure 3b should be used (a). A cut-down version of that board only allows front-end circuitry traces to go to the ADC's analog input pins (b).

A connector needs to be mounted at the converter’s pins. (Usually there’s enough copper to complete this task.) It helps to be creative at this stage to achieve a solid connection for that connector. Generally, the ADC’s exposed paddle, or “epad,” can be used for the ground connection from the converter itself. Only one-half of the differential traces is needed, assuming both front-end circuitry traces are equal and symmetrical. This board makes a “thru” measurement, which will be de-embedded from the populated board measurement.

The next step is to take the “thru” measurement on the de-embedding board (Board 2, Fig. 4b) to measure an S21 (Fig. 5). This file, which should be saved in touchstone format or an • .S2P file, will become the de-embedding file required to strip away all trace parasitics from the populated board.

Fig 5. Shown is the de-embedded trace impedance of the cut board in Figure 4b.

After that, simply connect the populated board (Board 1, Fig. 3b) to the network analyzer in a differential configuration. The board should have power and a clock applied to ensure the capture of any parasitic changes to the converter’s internal front-end design during the measurement process.

By “turning on” the populated board, the converter will seem as if it were in a typical application. During this measurement, de-embed the board parasitics measured from on the previous cut board on each port (each analog input trace) (Fig. 6).

 Fig 6. This curve illustrates the ADC's impedance with de-embedded traces.

This will ultimately subtract the board parasitics from the current ADC measurement, leaving only the package and internal front-end impedance to show through (Fig. 7).

Fig 7. This curve illustrates the ADC's impedance with de-embedded traces.

Converter Input Impedance: Mathematical Approach

Now, let’s do a little math and see if all that lab time was worth it. The internal input impedance of any converter can be modeled (Fig. 8). The network represents a good model of the input network’s ac performance in track mode, when the sample is taken.

Fig 8. The ac performance of the ADC's internal input network is shown here in track mode, when the sample is taken.

Typically, any datasheet will show some kind of static input impedance that’s differential with an R || C derived from simulation. This very simple model is shown in this manner to give a close approximation and make the math easy. Otherwise, if the equivalent impedance model also includes the sampling clock rate and duty cycle, small impedance variations can make the math much more difficult.

Also, note that these values are a reflection of the ADC’s internal circuitry during the sampling process in track mode—this is when the actual sample of the signal is taken. In hold mode, the sampling switch is open and isolates the input front-end circuitry from the internal sampling process or buffer.

If we derive the simple model (Fig. 8, again) and solve for the real and imaginary terms:

Z0 = R, Z1 = 1/s • C, s = j • 2 • π • f, f = frequency

ZTOTAL = 1/(1/Z0 + 1/Z1) = 1/(1/R + s • C) = 1/((1 + s • R • C)/R)) = R/(1 + s • R • C)

Now sub in for s and multiply by the complex conjugate:

ZTOTAL = R/(1 + j • 2 • π • f • R • C) = R/(1 + j • 2 • π • f • R • C) • ((1 – j • 2 • π • f • R • C)/(1 – j • 2 • π • f • R • C)) = (R –j • 2 • π • f • R2 • C)/(1 + (2 • π • f • R • C)2)

Now find the “real” and “imaginary” terms:

ZTOTAL = Real + j • Imag = R/(1 + (2 • π • f • R • C)2) + j • (–2 • π • f • R2 • C)/(1 + 2 • π • f • R • C)2)

Real = R/(1 + (2 • π • f • R • C)2) Imag = (–2 • π • f • R2 • C)/(1 + (2 • π • f • R • C)2)

This mathematical model aligns very well with the ac simulation in track mode (Figures 9 and Figure 10). The main source of error in this simple model is the settling level of the impedance at higher frequencies. Note that these values are usually derived through a set of simulations, which are spot on.

Fig 9. Shown is the "real" part of the converter input impedance curves, which compare measured, math, and simulation results.

Now, look at the measurement as shown in Figure 9 and Figure 10. All three curves aren’t exact, but close. That’s because some measurement error will always be present, and the simulations may not account for all the converter’s package parasitics. Thus, some mismatch is to be expected. Nonetheless, the curves are similar in shape and contour, giving a fairly good approximation of the converter’s impedance.

Fig 10. Shown is the "imaginary" part of the converter input impedance curves, which compare measured, math, and simulation results.

Be aware that a network analyzer’s ability to provide a faithful measurement is only ±10 times the characteristic impedance standard of the analyzer. So if the network analyzer’s characteristic impedance is 50 Ω, then a decent measurement is only achievable between 5 and 500 Ω. This is another reason why the simplified R||C values listed in the datasheet are preferred.

Converter Input Impedance Wrap-Up

Understanding converter impedance is an essential piece in designing signal chains. In the end, why shell out lots of money for expensive test equipment or go through the trouble of measuring the impedance if it isn’t really required? Rather, use the RC parallel combination impedance found in the datasheet and just apply a little math. This can yield a quick and easy way to acquire the converter’s impedance curve.

Also remember that process resistor tolerances can be as high as ±20%. Even after going through the arduous task of measuring the impedance of any device, input or output, it collects only one data point—unless, of course, many parts are being measured over several lots versus temperature and supply variations. Use the simulated R||C value in the datasheet. It provides enough information for the characteristic impedance over frequency, resulting in a properly functioning signal chain.

References

1. “Frequency Domain Response of Switched-Capacitor ADCs,” AN-742, Analog Devices Application Note.

2. “Improve the Design Of Your Passive Wideband ADC Front-End Network,” Electronic Design, March 2010.

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