The advent of the 90-nm CMOS processes enables a boatload of logic and memory within a single IC, measured in tens of millions of gates. The first-order thinking is that it's always possible to add a little more circuitry into the mix and eventually go to a complete system-on-a-chip. A telling statistic of this trend comes from the Fabless Semiconductor Association. It notes that over 75% of the new parts that association members will develop include analog and mixed-signal components.
Let's look at this carefully. Most analog functions comprise a few hundred to a few thousand transistors. If you include the passive resistors and capacitors, you might get a total count of 10,000 components. Therefore, you will put this analog circuitry into the digital chip and get the following characteristics:
The very fine-line processes only allow for fairly low-voltage supplies and signal swings, so accuracy and headroom suffer. The available libraries of analog and mixed-signal functions are fairly limited—tens of amplifier configurations, a half-dozen comparators, a couple of analog-to-digital and digital-to-analog converters, a phase-locked loop, and a voltage reference.
Take this limited palette of functions and put them into a process designed for digital logic. First you must figure out how to perform the chip layout. The analog functions may take up 10% to 15% of the total die area while constituting less than 1% of the transistors, and have very stringent layout restrictions—keep-outs, guard rings, no route-throughs, and so forth.
Take this handful of components and use a standard process plus the analog processing modules to get somewhat reasonable analog performance. This processing module will increase wafer manufacturing costs from 20% to 50%, plus add at least two masking steps to the standard CMOS process.
The mixed process will cause further detrimental effects to the yields in two ways. First, the process is more complex. So it will more likely have process and mask-induced faults. Second, digital testers usually can't test anything but very simple analog functions. Therefore, test will require at least one additional test insertion. Each test results in more yield loss, independent of test order.
The net result is a device that uses suboptimal parts in an expensive and lower yielding process. Due to the limited analog accuracy, the DSP functions need to perform much more signal processing, adding to the power consumption and programming complexity. The digital noise in the logic portions is omnipresent and nearly impossible to eliminate from the analog sections.
Alternatively, consider putting the low-noise, high-accuracy analog and mixed-signal components into a separate chip in a process that's optimized for analog functions. This chip can operate at fairly high voltages—5 to 30 V—which maps more closely to the range of signals to be processed, compared to the logic chip at 1.5 V. The "older" analog processes probably have libraries of many hundreds of analog and mixed-signal components. In addition to the higher operating voltages and greater device linearity, high precision or trimmable resistors are often available for the converters and references.
So you reduce noise and cost to get higher-fidelity analog circuitry and a small, high-yield part in a separate chip. If you go to a multichip package or to stacked die, it doesn't even add any additional pins or packages. This separation also reduces board layout problems by segregating analog and digital areas. This sounds like a reasonable trade to me.