Input Sampling Architectures in Analog-to-Digital Converters
By Kevin Tretter,
Microchip Technology Inc.
Today's analog system designers face many design challenges. Not only do designers need to select the proper integrated-circuit components, but they also must accurately predict the interactions of these components within the system. Analog-to-digital converters can pose an especially difficult challenge in this regard, offering a variety of different input sampling architectures that must be considered on the system level. This article will explore several common types of input sampling architectures and discuss the implications that each architecture has on the rest of the system.
A common solution found in many of today's CMOS A/D converters is the use of a switchedcapacitor structure to accomplish input sampling. In its most basic form, this input structure is composed of a relatively small capacitor and analog switches, as shown in Figure 1.
When the switches are configured in position 1, the sampling capacitor is charged to the voltage of the sampling node, in this case VS. The switches are then flipped to position 2, where the accumulated charge on the sampling capacitor is transferred to the rest of the sampling circuitry. The process then begins all over again.
An unbuffered switched-capacitor input, such as the one described above, can cause significant system-level issues. For example, the current required to charge the sampling capacitor to the appropriate voltage must be supplied from the external circuitry connected to the A/D-converter input. When the capacitor is switched to the sampling node (switch position 1, in Figure 1), a large amount of current is required to begin charging the capacitor. The magnitude of this instantaneous current is a function of the size of the sampling capacitor, the frequency at which the capacitor is switched, and the voltage present on the sampling node.
This switching current is described by the following equation:
iin = CVf
where C is the capacitance of the sampling capacitor, V is the voltage present on the sampling node (in this example denoted as VS), and f is the frequency at which the sampling switch is turned on and off. This switching current results in high current spikes on the sampling node, as illustrated in Figure 1.
The implications of this switching current must be considered when designing the analog circuitry in front of the A/D converter. As this current passes through any resistance, a voltage drop will occur, resulting in a voltage error at the sampling node of the A/D converter. The error can become substantial if a high impedance sensor or a high impedance filter is connected to the input of the converter.
For example, assume that a resistor is placed in front of the A/D converter to provide sensor isolation and improve electrostatic discharge (ESD) protection, as shown in Figure 2. In this example, the sampling capacitor is 10 pF and is being switched at 1 MHz. Using the equation above, the instantaneous current is approximately 25 µA. As this instantaneous current passes through the 10-k½ resistor, an error voltage of 250 mV will occur on the sampling node. This is a worst-case approximation, as the sampling node may settle prior to the next sample cycle. This settling time is dependent on the RC time constant formed by the 10-k½ resistor and the sampling capacitor, plus any parasitic capacitance on the input of the A/D converter. Parasitic capacitance can be due to the leads of the A/D converter, trace lengths on the circuit board and internal MOS switch capacitance. An external buffer circuit may be required to supply the needed current and ensure that the sampling node is properly settled to maintain linearity.
However, at higher switching frequencies the amplifier output impedance will increase. Care must be taken when selecting the amplifier and associated circuitry to account for this instantaneous switching current.
In order to minimize the instantaneous current requirements of the external circuitry, an internal buffer can be implemented, as shown in Figure 3. In this implementation, the analog switches combine to form three different states. In position 1, the sampling capacitor is quickly charged to the sampling node voltage (in this example VS), plus or minus the buffer offset (VOS). The instantaneous current required to charge the capacitor during this phase is provided by the internal buffer circuitry. The internal buffer can be optimally designed to provide a low impedance output at the required switching frequency that can properly charge the capacitor in the allotted time. The switches are then reconfigured to create a connection at position 2 in the figure. During this phase, the sampling capacitor is directly connected to the sampling node of the A/D converter. The sampling capacitor is then charged or discharged such that the voltage on the capacitor is equal to the voltage at the sampling node. Some switching current may still be present, but less current will be required from the external circuitry, since the capacitor voltage is already charged to within the offset voltage of the internal buffer. Finally, the analog switches are configured to position 3, allowing the sampled voltage to be transferred to the rest of the sampling circuitry. The advantage of a buffered switched-capacitor input is a significant reduction in the instantaneous current required from the circuitry external to the A/D converter. In the earlier example, the sampling capacitor is 10 pF and the switching frequency is 1 MHz. Assuming the internal buffer has an offset of 10 mV, this would result in an instantaneous current of only 100 nA, which is 250 times less than the instantaneous current in the unbuffered sampling input.
In some cases, a fixed or programmable gain amplifier is integrated into the same silicon in front of the A/D converter. The amplifier not only helps to reduce the switching current that must be supplied by the external circuitry, but also provides amplification of the analog signal. A chopperstabilized amplifier can also be implementedto reduce the 1/f noise, sometimes referred to as "flicker noise." This low-frequency noise is due to the surface states in the channel of the MOS transistors inherent to the process technology. Chopping can remove the 1/f noise and reduce the external current requirements. However, some input instantaneous current will still be seen, due to mismatches in the MOS switches.
Regardless of the sampling architecture, A/D converters must implement some form of ESD protection. For CMOS solutions, this protection typically takes the form of clamping diodes, as shown in Figure 4. These clamping diodes effectively limit the voltage that can be placed on the transistors internal to the converter. If the input voltage goes above or below the supply rails by more than a diode drop (typically 0.7V), the diode will begin to conduct current and limit the voltage. However, these clamping diodes also exhibit current leakage, which must be considered when designing the analog input circuitry. Although this leakage current is typically small, perhaps a couple of Pico amperes, the current can increase dramatically as a function of temperature.
As A/D converters continue to advance, it is critical for system designers to fully understand the input structure utilized and the effect that this structure has on the external circuitry. In the examples above, a simple switched-capacitor input was examined. The switching current requirements can greatly affect the overall system performance, and the external circuitry must be designed accordingly. An integrated buffer or amplifier can greatly reduce this switching current, simplifying the circuit design external to the A/D converter. ESD protection circuitry will also affect external current requirements and can vary greatly over temperature.
Kevin Tretter is a Senior Product Marketing Engineer for the Analog and Interface Products Division of Microchip Technology Inc. He can be reached by e-mail at [email protected].
Company: MICROCHIP TECHNOLOGY INC.
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