Inside Silicon Labs’ CMEMS Resonators

Inside Silicon Labs’ CMEMS Resonators

MEMS resonators for clocking ICs differ. Silicon Labs has created a flat plate built of silicon dioxide ans silicon-germanium.

Silicon Labs’ process starts with standard, passivated, and planarized CMOS wafers. Polycrystalline silicon-germanium (Poly-SiGe) and pure germanium (Ge) are surface micro-machined to create integrated MEMS devices on top of the CMOS circuitry.

Silicon Labs isn’t saying precisely how its process technology can create microstructures without destroying the underlying CMOS IC. But the company will show photos of the resonator structure (Fig. 1). What one sees is a square plate with slits of silicon dioxide. Those slits are a key component of Silicon Labs’ intellectual property. The company says the technique avoids the temperature sensitivity of other companies’ processes.

1. Silicon Labs took an entirely different approach in its resonator, a flat plate made of silicon germanium and silicon dioxide.
1. Silicon Labs took an entirely different approach in its resonator, a flat plate made of silicon germanium and silicon dioxide.

Silicon Labs says this comes about because the CMEMS resonator is fabricated from both polymorphous SiGe and silicon dioxide (SiO2). The temperature coefficient of the SiO2 compensates for the temperature coefficient of the SiGe, and the resulting resonator temperature coefficient is in single-digit ppms/°C. As with any semiconductor clock, these MEMS oscillators use this passively compensated resonator for a reference frequency with which to drive a cost-optimized, power-efficient digital frequency-locked loop (FLL) (Fig. 2).

2. On the analog side of their devices, both SiTime and Silicon Labs use frequency-locked loops referenced to the resonator for control. SiTime uses a fractional-N architecture. This version, from Silicon Labs, uses a conventional ring architecture.
2. On the analog side of their devices, both SiTime and Silicon Labs use frequency-locked loops referenced to the resonator for control. SiTime uses a fractional-N architecture. This version, from Silicon Labs, uses a conventional ring architecture.

The FLL uses the MEMS reference frequency along with a divided signal from an on-chip voltage-controlled oscillator to drive a frequency comparator that generates frequency error values and feeds them to the FLL’s digital loop filter. The FLL also handles temperature compensation, using an on-chip sensor. For more, see “CMEMS Oscillator Architecture.” 

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