Electronic Design

Interface 20-Bit Sigma-Delta ADCs Through A PC's Parallel Port

In most sigma-delta analog-to-digital converter (ADC) applications, the serial data transfer occurs through a serial port. A microcontroller configures the serial port as required—setting the baud rate and stop/start bits, initializing the serial port, and so on.

In this simple, inexpensive design, the ADC, an AD7703, connects to the PC via its parallel port (Fig. 1). The controlling software is written in the graphic language LabVIEW version 6.0, which collects the ADC's serial data through one of the bits in the LPT1 Status port (0x379)—i.e., through pin 15 (LPT port ERROR input) of the DB-25 connector. Software can be written in any higher language like Turbo "C," C++, VB, VC, etc. The AD7703 is connected in the synchronous external-clock (SEC) mode to permit the direct interfacing of the synchronous serial data transfer to the host PC.

Once the ADC completes the conversion, its Data Ready (--DRDY) pin goes from high to low. The DRDY output of the ADC is connected to the PC's LPT1 port, pin 10 (Acknowledge input). The controlling software senses the DRDY and sets the ADC's chip select, --CS, through pin 1 (DATA Strobe output) to low and receives the most significant bit (MSB) from the ADC. After receiving the MSB, it generates a Serial Clock output (SCLK) through pin 14 (Auto Line Feed output) to acquire the remaining 19 bits from the ADC.

Once all 20 bits are received, the --CS is set to high, enabling the ADC to set the new data in its three-state output buffer. This sequence will continue, and the acquired data will be displayed in both the digital and analog panel meters on the LabVIEW front panel (Fig. 2).

As the serial 20-bit data is acquired through pin 15, the controlling software shifts most of the bits left as per the bit position. Some of the bits are shifted right, setting other unwanted bits to zero. Finally, a logic OR function of the 20-byte word produces the 20-bit pattern of the acquired signal.

For example, the MSB 20th bit will appear as the first bit for transfer. This bit must be set as the 20th position of the word. Therefore, the data received through the fourth (D3) bit has to be shifted 16 positions left to form it as a 20th bit.

Similarly, the next MSB received through this D3 bit is shifted 15 positions left to assign it as a 19th bit, and so on. In this sequence of data fashioning, once the fourth bit of the 20-bit pattern (LSB 4) has appeared, it doesn't need any shifting because it's an actual D3 bit. Likewise, for the third bit (D2), shifting is required to the right by one position, and the D1 and D0 bits require right shifting by two and three positions, respectively.

This way of shifting and finally doing a logical OR produces the exact 20-bit data pattern from the serial data received through one pin of the parallel port. The LabVIEW Virtual Instrument program provides a time delay of 125 µs between SCLK and the serial data read (i.e., inport function). This sets the data transfer rate to 4 kHz, the maximum suggested by the manufacturer. This time delay will let the read cycle read exactly at the midpoint of the data bit to avoid an improper data read.

Designers can use this simple and low-cost approach with any sigma-delta ADC. But ADCs that include a start bit and a stop bit in each byte will require a slight program modification.

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