It's A Jungle Up There: Radiation Effects In CMOS Devices

Aug. 23, 2004
For a place we think of as the ultimate void, space is populated with many high-energy particles that can damage semiconductor devices. There are electrons and protons in the Van Allen belts, galactic cosmic rays (about 85% protons, 14% alpha...

For a place we think of as the ultimate void, space is populated with many high-energy particles that can damage semiconductor devices. There are electrons and protons in the Van Allen belts, galactic cosmic rays (about 85% protons, 14% alpha particles, and 1% heavy ions), and cosmic rays from solar flares (which also contain ultraviolet and X-rays). There are also secondary particles from cosmic rays that have reached the earth's surface.

Neutrons, protons, alpha particles, heavy ions, and very high-energy gamma rays cause defects by displacing atoms in the crystal lattice. Charged particles and gammas create ionization, which can change device parameters such as threshold voltages and leakage currents.

Single-event upsets (SEUs) are transients induced by charged particles (usually from the radiation belts or from cosmic rays) that lose energy by ionizing the crystal lattice, leaving a wake of electron-hole pairs. They can generally be overcome by a reset or a rewrite. However, an SEU becomes a single-event functional interrupt (SEFI) when the device's control circuitry places it into a test mode, halt, or undefined state. Unlike SEUs, SEFIs need a power-reset to recover. Single-event transients (SETs) are also recoverable. They occur when charge collection from an ionization event creates a spurious signal that propagates through the circuit.

Single-event latch-ups (SELs) occur when a single event causes a high current state. They may destroy the device, or they may be recoverable with a power-reset.

The Honeywell/Cypress process is being developed on SOI wafers from Soitec, based in Grenoble, France. In that company's proprietary Smart Cut technique, ultra-thin silicon slices of crystalline silicon are transferred onto a second surface. Thicknesses can range from 20 nm up to several microns for the top silicon, and buried oxides can range from less than 100 nm up to a few microns in thickness.

Where bulk-CMOS devices can only withstand total dose levels between 5 and 10 krad, SOI can handle levels many orders of magnitude greater. Honeywell SSEC defines its radiation levels as strategic rad-hard, rad-hard, and rad-tolerant. See the table which describes the differences.

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