How does an analog foundry reduce power consumption in an RF mixed-signal process while accommodating for the differences in scalability between logic and analog circuit elements? Jazz Semiconductor plans to do it with a 0.13-µm silicon-germanium (SiGe) biCMOS technology that combines 90-GHz SiGe transistors with the company s existing 1.2-V, 0.13-µm digital CMOS platform.
A 2.8-µm thick top metal layer boosts inductor performance. Also part of the new SBL13 process geometry are a stacked 5.6-fF/µm2 metal-insulator-metal capacitor that lets designers aggressively scale the capacitance area. Late last month, Jazz began offering process design kits for SBL13.
In terms of mask count, and therefore implementation cost, the new six-layer process resembles an industry-standard 0.13-µm RFC-MOS process. But instead, its back end is made out of aluminum, which is more economical than copper. SBL13 also uses a 1.2/3.3-V dual gate oxide process to form the base CMOS. It then adds the SiGe transistors.
There are three npn options: standard, high-speed, and high-voltage. The standard npns have a 67-GHz cutoff frequency, a 123-GHz fmax, and a 3.5-V breakdown rating. The high-frequency versions offer 90-GHz, ft, 100-GHz fmax, and 2.4-V BVceo. The high-voltage versions boast 40-GHz, ft, 60-GHz fmax, and 6-V BVceo. (The high-voltage option adds an additional mask layer.)
Jazz Semiconductor plans to add a pnp with a cutoff frequency in the 20- to 30-GHz range in the future.