These tradeoffs include bandwidth, input drive, impedance, and performance. The topology is also important, i.e., amplifier versus transformer coupled input as well as the ADC’s architecture, buffered versus unbuffered. Numerous papers provide insight on how to choose between these tradeoffs.
System design specifications should dictate which topologies and tradeoffs to use to build the kind of signal chain and front-end ADC development to be designed. Even after the design is chosen, don’t go throwing all the hard work away. Think about the limitations that could be imposed if the signals are slightly unbalanced. Yes, that’s correct. A major effect is that the dynamic range will be limited.
The birth or rise of even-order distortions is usually dictated through one or many signal-chain imbalances. In a perfect world, even-order distortions (second, fourth, sixth harmonics, etc.) wouldn’t exist as long as perfect symmetry is maintained throughout the signal chain and the parts that are used.
Odd-order distortions (third, fifth, seventh harmonics, etc.) manifest themselves through the nonlinearity of each device and the headroom or bias applied. Your design will still work, but the level of performance will be unknown unless you understand where the limitations are created.
Common-mode voltage issues between interfaces are some of the most prevalent causing even-order distortion. Even if the last stage is perfectly balanced, a common-mode voltage imbalance further down the signal chain could be causing the issue that the converter will see in the end.
It doesn’t matter if your design is ac or dc coupled. Each interface stage needs a rock-solid common-mode voltage to have symmetrical differential signals enter the ADC’s inputs. If not, then the converter’s output spectrum will over-range, under-range, or just look dirty. This is assuming you’re working with bipolar signals and single supplies.
Tolerances in passive components can be a killer in performance too. This can be seen in summing nodes in the feedback loop of an amplifier and multi-pole anti-aliasing filters between amplifiers and converters. Simple mismatches here can be seen in the math.
A common-mode voltage mismatch (Fig. 1) can develop if the component tolerances of RG and RF aren’t tight.
Any mismatch here will cause the summing node VACM to be slightly different as these resistors drift over the tolerance itself, over the temperature variation, and over life. A difference in VACM will cause VIP and VIN to be different on the amplifier’s outputs, giving rise to second-order distortion.
To combat this, make sure the component tolerances are low (<1%). If accuracy is important, some specialized resistor packs offer low ppm drifts and tight tracking tolerances. That’s one of the reasons why Analog Devices puts matched resistor gain networks inside our high-speed amplifiers.
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Keeping component tolerances low is essential, and variations in even-order distortion can be seen when anti-aliasing filters are designed too. In most communication applications, the ADC has a multi-pole cascaded filter designed to have a narrow bandwidth (20 to 40 MHz), so you can imagine the number of components it might take to build up a filter like this (with 10-piece components if the filter is differential).
Obviously, the more components, the more tolerance variations and mismatch errors add up between components. Inductors are known to be the culprit here, so keeping these tolerances low is key. Inductors also can have solderability issues if the thermal profile at the assembly house isn’t right. Poor contacts have sometimes proven to be the culprit here, even when the solder joints look pretty with a high buff sheen.
If you aren’t careful, you can still lose it all during the layout stage. Keep the layout tight and symmetrical throughout the signal chain. If not, second-order distortions will arise. In a typical front-end balun arrangement used to help improve on phase imbalance, for example, even the slight mismatches can cause substantial degradation.
Other cases have involved mismatch in filter traces and other interfaces between adjoining signal-chain components. Keep the layout symmetrical when using high IF frequencies, but don’t beat up the CAD operator to match everything to the nth degree.
Also, be mindful of any tradeoffs that are made during the layout phase. Otherwise, asymmetrical paths, whether they’re in length or in parasitic differences, can cause a delta in phase between two differential signals when they arrive at the converter analog inputs.
How immune is the converter itself to imbalance? We’ll never have perfect balance throughout the signal chain, so how tolerant is the converter to imbalance? Sure, the entire problem cannot be pushed onto the front-end signal-chain components alone. There will be some finite amount of imbalance, whether it’s in component tolerance, layout constraints, or some other factor. But how resilient is the converter to these imbalances, and will it make a significant difference in distortion?
In recent testing, we found that by locking two independent signal sources together, we could shift the phase by several degrees to test the ADC’s tolerance to imbalanced signals. First off, the expectation in performing such a test would not only prove how good the converter is over frequency, but also how well the balance can be controlled in the layout of the IC itself.
As frequency is increased, the general trend is that the phase imbalance of any two signals is inevitably going to happen. So, we should expect the trend to get worse as frequency is increased. Second, as phase imbalance gets bigger, the even-order distortions will rise automatically. So if we look at the two trends together during the test, we should see a ramp-like curve develop (Fig. 2).
This tells us that any signal imbalance has about a 3° tolerance to mismatch over frequency before a huge impact in converter performance (<5 dB) is seen. Any higher imbalance will begin to degrade the performance rapidly. Also, the third-order distortion is relatively flat as frequency is increased, and phase imbalance is forcibly mismatched. This again underscores the point that imbalanced signals are the leading factor to even-order distortions as opposed to odds.
Be mindful of imbalance and symmetry in your signal-chain design, as this will maximize your system performance. Without careful layout, component selection, and common-mode voltage mismatches being kept at a minimum, the system will suffer, at least in the case of even-order distortion. And if you think the converter is doing its job, it is, but only to a degree—no pun intended.