Electronic Design
Mine These High-Speed ADC Layout Nuggets For Design Gold

Mine These High-Speed ADC Layout Nuggets For Design Gold

 

 

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High-speed design can be overlooked or overly vital. The layout of the system board has become an integral part of the design itself. Therefore, it is paramount that we understand the mechanisms that affect the performance of our high-speed signal chain designs.

As engineers, though, we tend to “make” more problems than we really have. So, try not to be too critical and push your CAD engineer to the brink of insanity for things that don’t buy your design any improvement in performance.

Don’t Forget The Epad

The epad sometimes becomes an overlooked item that’s essential in getting the most performance out of the signal chain and heat out of the device. The epad, or pin 0 as we call it at ADI, is the paddle found underneath most parts today. This is an important connection, as it generally ties all internal grounds from the die to a central point under the part.

Have you noticed a lack of ground pins in many converters and amplifiers today? The epad is why. The key is to get this pin tied down—i.e., soldered—well to the printed circuit board (PCB) to make a robust electrical and thermal connection. If not, there can be all sorts of havoc in your system design.

There are basically three steps to achieving the best connection, electrically and thermally, with the epad. First, if possible, replicate the epad on each PCB layer. By doing so you create a thick thermal connection to all grounds and ground layers so the heat can dissipate and spread out quickly.

This is pertinent for those high-power parts and for applications that have high channel counts. Electrically this provides a nice equal connection to all the ground layers. You can even replicate the epad on the bottom layer (Fig. 1). This can serve as a thermal relief ground point for decoupling and a placeholder to attach a heatsink on the bottom side.

Second, partition the epad into equal segments like a checkerboard. You can do this by one of two ways: using a silkscreen crosshatch on the open epad or solder mask. This ensures a robust connection between the part and the PCB. During the reflow assembly process, there’s no way to guarantee how the solder paste will flow and ultimately connect the part to the PCB.

What can happen is that the connection will be present but not evenly distributed. You may only get one connection and that connection could be small or, worse yet, in a corner. By dicing up the epad into smaller partitions you can ensure a connection point in each separate area, giving you a more robust and evenly connected epad (Figure 2 and Figure 3).

Finally, make sure each of those partitions has via connections to ground. Usually the partition is big enough so several vias can be placed. Make sure each of these vias is filled with solder paste or epoxy before assembly. This important step will ensure the epad solder paste won’t be reflowed into those via voids and reduce the chance for a proper connection.

Decoupling & Plane Capacitance

Sometimes we lose sight of why we use decoupling. Simply spreading many value capacitors across your board gives way to a lower impedance supply connection to ground. But the question still remains—just how many capacitors do you need?

A lot of literature says you need to use many capacitors and many values to lower the power delivery system’s (PDS) impedance. But that isn’t entirely true. Really, you only need to select the right values and the right “kinds” of capacitors to make the PDS impedance low.

Say we want to design a 10-m? reference plane. If many capacitor values are employed on a system board, you can lower the impedance across a 500-MHz frequency range, as shown by the red curve in Figure 4.

However, look at the green curve. Here we only have 0.1-µF and 10-µF capacitors used on the same design. This proves that if the right capacitors are used, then not as many capacitor values are needed. This also helps save on placement and bill of materials (BOM) costs.

Not all capacitors are created equal, though. Make, size, and style matter, even from the same vendor. If the right capacitors aren’t used, whether it’s many capacitors or a few different types, the result can have the opposite effect on your PDS.

This can cause inductance loops due to the placement of capacitors or just by using different capacitor makes and models that respond differently over frequency in the system and resonate against each other (Fig. 5).

Taking the time to understand the frequency response of the capacitor types that are employed in your system is crucial. Don’t undo all the hard work you put into designing a low-impedance PDS system by using just any capacitor.

To design a good PDS, you need to use a variety of capacitances (Fig. 4, again). Typical capacitor values used on the PCB only keep the impedance low between the frequency range of dc, or near dc, to roughly 500 MHz. Above 500 MHz, the capacitance is dictated by the internal capacitance developed by the PCB. Are you stacking your power and ground plane tightly?

To do this, design a PCB stack that supports a large plane capacitance. For example, a six-layer stack may comprise a top signal, ground1, power1, power2, ground2, and bottom signal. Specify ground1 and power1 to be close in the stack. Separating them by 2 mils to 4 mils forms an inherent high-frequency plane capacitor.

The best part about this capacitor is that it’s free. You just need to specify it in the PCB fabrication notes. If the power planes must be divided, with multiple VDD rails on the same plane, use as much of the plane as possible. Don’t leave voids, but be mindful of sensitive circuitry as well. This will maximize the capacitance for that VDD plane.

If the design allows for extra layers (from six to eight in our example) put two extra ground planes between power1 and power2, doubling the inherent capacitance in the stack given the same 2- to 3-mil core spacing (Fig. 6). This can be much easier to design in then to add more discrete high-frequency capacitors to keep the impedance low.

Often overlooked, the task of the PDS is critical to minimize the voltage ripple that occurs in response to supply current demand. All circuits require current—some more than others, and some at faster rates than others. A low-impedance power or ground plane with adequate decoupling and a good PCB stack will minimize the voltage ripple that occurs as a result of the circuit’s current demands.

If the system design has 1 A of switching current and the PDS is designed to have a 10-m? impedance, based on the decoupling strategy used, the maximum voltage ripple will be 10 mV. It’s that simple: V = IR.

With the perfect PCB stackup, the high-frequency range can be covered, while the use of traditional decoupling at both the entry point where the power plane originates and around the devices that run at high power or surge currents can cover the lower frequency range (<500 MHz). This will ensure the lowest PDS impedance across the entire frequency range.

It isn’t necessary to sprinkle capacitors everywhere and place them right up against every IC, breaking all kinds of manufacturing rules. If these kinds of drastic measures are required, then something else is going on in the circuit.

Plane Coupling

Some layouts inevitably will have one circuit plane overlapping another (Fig. 7). In some of these cases, it might be a sensitive analog plane (power or ground or signal, whatever the case) and the next layer underneath is a noisy digital plane. Most designers would say that it doesn’t matter because the plane is on another layer. So, here is a simple test to try.

Take one of those layers and inject a signal on either plane. Now connect the other layer that cross-couples that adjacent layer to a spectrum analyzer. Can you see how much signal is coupling through to the adjacent layer? Even if they are separated by 40 mils, it’s still a capacitor in some sense, and therefore it will still couple signal through to the adjacent plane at some frequency (Fig. 8).

Let’s say a noisy digital plane on one layer has a 1-V signal that switches at a high speed. This means the other layer will “see” 1 mV of coupling (~60-dB isolation). To a 12-bit analog-to-digital converter (ADC) with a 2-V p-p full-scale swing, this is 2 least significant bits (LSBs) of coupling. This may be fine for your particular system, but keep in mind that as you go up 2 bits, from 12 to 14 bits, the sensitivity only quadruples. That’s 8 LSBs.

Ignoring this type of cross-plane coupling will probably neither make the system fail nor cripple the design. All that’s being pointed out here is that coupling exists between two planes more than what might be imagined.

Keep this in mind when noisy spurs are seen coupling in the frequency spectrum of interest. Sometimes layouts dictate unintended signals or planes to be cross-coupled to a different layer. Remember this when debugging your sensitive systems. The issue may lay one layer below.

Splitting Grounds

The most common question that’s asked by analog signal chain designers around the globe is if the ground plane should be split into an AGND and DGND ground plane when using an ADC. The short answer is that it depends.

The long answer is not usually. In most situations a split ground plane can cause more harm than good, as blindly splitting the ground plane only serves to increase the inductance for the return current. Remember the equation V = L(di/dt)? As the inductance is increased, so is the voltage noise.

As the inductance increases, so does the PDS impedance, which you just worked so hard to keep low. There is only so much one can do about increasing switching currents, as the request for increasing ADC sampling rates continue. So unless you have a reason to split your ground plane, keep those grounds connected.

Good circuit partitioning is key to not splitting ground planes (Fig. 9). Notice that if a layout allows you to

keep the respective circuits in their own areas, then there’s no need to split the ground. Partitioning this way allows for a star ground that, therefore, keeps return currents localized to that particular circuit section. One split example is when a form factor restriction prohibits good layout partitioning. This could be because the dirty bus supplies or noisy digital circuits must be located in certain areas to conform with a legacy design or form factor. In that case, splitting the ground plane may make the difference in achieving good performance.

However, to make the overall design work, a bridge or tie point is required to connect the grounds together somewhere on the board. With that being the case, spread the tie points evenly across the ground plane split.

One tie point on the PCB often ends up being the optimum place for the return current to pass without reducing performance or forcing return currents to couple to sensitive circuitry. If this tie point is at or near or under the converter, you didn’t need to split the grounds in the first place.

Conclusion

Layout considerations can always be confusing because there are a lot of opinions on what is best. Techniques and philosophy tend to become part of the ”design culture” of the company. While engineers tend to use what worked in their previous designs, possibly influenced by the “old analog guru” in the back office, designers often are reluctant to change or try new things because of time-to-market pressures. This leaves them in the position of weighing tradeoffs with risk until something really does go wrong in the system.

At the evaluation board, module, and system level, a simple single ground works best in all cases. Good circuit partitioning is key. This also extends into plane and adjacent layer layout. Keep in mind that cross coupling can occur if sensitive planes are just above those noisy digital planes.

Assembly is important too. Use the fabrication notes given to the PCB house or assembly house to your advantage to ensure that the connection between the IC’s epad and PCB is solid. All too many times, poor assembly leads to poor system performance.

Decoupling close to both the power plane entry point and the VDD pins of the converter is always good, though. For added, inherent high-frequency decoupling, take advantage of tight power and ground plains of 4 mils or less. There is no extra cost for this except for the extra five minutes it will take to update your PCB fabrication notes.

There is no way to cover all the specifics when designing a high-speed, high-resolution converter layout. Each application is different and sometimes unique. However, these key points will be useful to designers in better understanding their future system designs.


References

1. Analog-Digital Conversion: Seminar Series, Walt Kester, Analog-Digital Conversion, Analog Devices, 2004, ISBN 0-916550-27-3; also available as The Data Conversion Handbook, Elsevier/Newnes, 2005, ISBN 0-7506-7841-0

2. AN-772: Gary Griffin, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP)

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