Electronic Design

Mixed-Signal Process Delivers EEPROMs To Analog ICs

A process collaboration deal between AMI Semiconductor and Intersil Inc. has yielded a mixed-signal process that incorporates electrically erasable memory with no extra process steps. The process can be used in systems with voltages as high as 20 V.

In a previous deal with Intersil in 2003, AMI installed one of Intersil's important manufacturing processes to provide a second source for various products. At that time, the standard AMIS mixed-signal processes were introduced to Intersil's design teams. The first Intersil designs implemented in the standard processes have now reached production status.

One of the key process attributes leveraged by Intersil's designers is the availability of electrically erasable memory in a submicron process. The AMIS process requires no added steps to implement the EEPROM storage cells, providing Intersil with a low-cost, nonvolatile memory with no added process complexity.

Known as NASTEE (no added step electrically erasable), the process can be used to provide reprogrammable elements in a mixed-signal design. This lets designers easily incorporate small memory arrays in the mixed-signal circuits. These arrays can then be used to hold trim and calibration data for the mixed-signal functions or hold chip identification information.

Unlike laser or fusible link trimming, NASTEE allows continued recalibration of circuits after they have been installed in a system-level application. Versions of the process are now available to other companies as well.

AMI Semiconductor
www.amis.com

Intersil Inc.
www.intersil.com

TAGS: Intersil
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