With high-performance monolithic rms converters available, why would anyone design one? Simple: No commercially available IC, running from a single power rail, can accurately convert signals with a dc component. Nor can any IC accommodate signals that must be galvanically isolated from ground. The rms converter described does both.
The trick that makes this possible is an optically isolated rectifier input circuit (see the figure). Input voltage Vin, applied to full-wave bridge D1-D4 and LED E2, produces LED current Ie2 = (abs(Vin) − Vd)/R1 = abs(Vin)/R1 − Vd/R1, where Vd = the sum of diode and LED voltage drops. The coupled gain of the E2:P2 optical pair results in photocurrent Ip2. To balance Ip2, A1 modulates Q3’s collector current Iq3, thereby Ie1 and the E1:P1 optical pair to force Ip1 = Ip2. Due to the channel tracking that exists in a multichannel opto like the PS2501-2, when Ip2 = Ip1, we can approximate Ie2 = Ie1. LED and rectifier diode voltages will also match well, so Ie1 = Iq3 −Vd/R1. Thus, Iq3 = Ie2 + Vd/R1 = abs(Vin)/R1, making Iq3 an accurate measure of Vin that’s (almost) independent of diode voltage drops! Admittedly, this compensation only works for Vin >> Vd, but that’s good enough to maintain 1% linearity for input voltages as low as 10 V rms.
With Iq3 = abs(Vin/R1), there remains the matter of rms conversion of Iq3. This computation is based on the log relationship between Vbe and collector current in Q1-Q5; the equality of this relationship among the five transistors in the LM3046 monolithic array; and the approximation that, for high beta transistors, Ic = Ie. Therefore, at any given temperature, there exist constants A and B such that Vbe3 = A*log(Iq3) + B and Vbe1 = Vbe2 = A*log(Iq3/2) + B.
Thus, (Vbe3 + Vbe1) = A\[log(Iq3) + log(Iq3)/2\] + 2B. Since adding logarithms is equivalent to multiplication, (Vbe3 + Vbe1) = A*log(Iq32/2) + 2B. Due to the topology of the circuit and the action of unity-gain buffer A2, (Vb3 + Vb1) = (Vbe4 + Vbe5). Then A*log(Iq32/2) + 2B = A*log(Iq4*Iq5) + 2B. Cancelling A’s and B’s and taking antilogs: Iq3 2/2 = Iq4 * 1q5. Capacitor C2 makes Iq5 = the time average of Iq4 and therefore Iq4 * avg(Iq4) = Iq32/2. Averaging both sides gives avg(Iq4*avg(Iq4)) = avg (Iq32/2), and thus avg(Iq4)2 = avg(Iq32/2). Taking square roots of both sides yields: avg(Iq4) = root(avg(Iq32/2)). Equivalently, Iq5 = RMS(Iq3)/sqr(2). Finally, because Iq3 = abs(Vin)/R1 and Vout = Iq5 *R3, we have at last: Vout = (R3/R1) * RMS(Vin)/sqr(2).
The prototype, with V+ = 9 V and R3/R1 scaled for a full-scale Vin of 125 V and output of 5 V, demonstrated better than 1% accuracy for Vin > 10 V and input frequencies up to 10 kHz. The circuit works accurately with supply voltages from 5 V to 15 V, but due to the way the voltage drops of D5, D6, E1, Q1, Q2, Q3, and R3 add up, Vout(max) is approximately (V+ − 4 V). So, V+ = 9 V is the minimum, consistent with a 5-V full-scale Vout. Current demand is modest at less than 2 mA.