With high-performance monolithic rms converters available, why would anyone design one? Simple: No commercially available IC, running from a single power rail, can accurately convert signals with a dc component. Nor can any IC accommodate signals that must be galvanically isolated from ground. The rms converter described does both.

The trick that makes this possible is an optically isolated rectifier input circuit (see the figure). Input voltage V_{in}, applied to full-wave bridge D1-D4 and LED E2, produces LED current I_{e2} = (abs(V_{in}) − V_{d})/R1 = abs(V_{in})/R1 − V_{d}/R1, where V_{d} = the sum of diode and LED voltage drops. The coupled gain of the E2:P2 optical pair results in photocurrent I_{p2}. To balance I_{p2}, A1 modulates Q3’s collector current I_{q3}, thereby I_{e1} and the E1:P1 optical pair to force I_{p1} = I_{p2}. Due to the channel tracking that exists in a multichannel opto like the PS2501-2, when I_{p2} = I_{p1}, we can approximate I_{e2} = I_{e1}. LED and rectifier diode voltages will also match well, so I_{e1} = I_{q3} −V_{d}/R1. Thus, I_{q3} = I_{e2} + V_{d}/R1 = abs(V_{in})/R1, making I_{q3} an accurate measure of V_{in} that’s (almost) independent of diode voltage drops! Admittedly, this compensation only works for V_{in} >> V_{d}, but that’s good enough to maintain 1% linearity for input voltages as low as 10 V rms.

With I_{q3} = abs(V_{in}/R1), there remains the matter of rms conversion of I_{q3}. This computation is based on the log relationship between V_{be} and collector current in Q1-Q5; the equality of this relationship among the five transistors in the LM3046 monolithic array; and the approximation that, for high beta transistors, I_{c} = I_{e}. Therefore, at any given temperature, there exist constants A and B such that V_{be3} = A*log(I_{q3}) + B and V_{be1} = V_{be2} = A*log(I_{q3}/2) + B.

Thus, (V_{be3} + V_{be1}) = A\[log(I_{q3}) + log(I_{q3})/2\] + 2B. Since adding logarithms is equivalent to multiplication, (V_{be3} + V_{be1}) = A*log(I_{q3}^{2}/2) + 2B. Due to the topology of the circuit and the action of unity-gain buffer A2, (Vb3 + Vb1) = (V_{be4} + V_{be5}). Then A*log(I_{q3}^{2}/2) + 2B = A*log(I_{q4}*I_{q5}) + 2B. Cancelling A’s and B’s and taking antilogs: I_{q3} 2/2 = I_{q4} * 1q5. Capacitor C2 makes I_{q5} = the time average of I_{q4} and therefore I_{q4} * avg(I_{q4}) = I_{q3}^{2}/2. Averaging both sides gives avg(I_{q4}*avg(I_{q4})) = avg (I_{q3}^{2}/2), and thus avg(I_{q4})^{2} = avg(I_{q3}^{2}/2). Taking square roots of both sides yields: avg(I_{q4}) = root(avg(I_{q3}^{2}/2)). Equivalently, I_{q5} = RMS(I_{q3})/sqr(2). Finally, because I_{q3} = abs(V_{in})/R1 and V_{out} = I_{q5} *R3, we have at last: V_{out} = (R3/R1) * RMS(V_{in})/sqr(2).

The prototype, with V+ = 9 V and R3/R1 scaled for a full-scale V_{in} of 125 V and output of 5 V, demonstrated better than 1% accuracy for V_{in} > 10 V and input frequencies up to 10 kHz. The circuit works accurately with supply voltages from 5 V to 15 V, but due to the way the voltage drops of D5, D6, E1, Q1, Q2, Q3, and R3 add up, V_{out(max)} is approximately (V+ − 4 V). So, V+ = 9 V is the minimum, consistent with a 5-V full-scale V_{out}. Current demand is modest at less than 2 mA.