Optically isolated input, single-supply true-RMS converter

With high-performance monolithic rms converters available, why would anyone design one? Simple: No commercially available IC, running from a single power rail, can accurately convert signals with a dc component. Nor can any IC accommodate signals that must be galvanically isolated from ground. The rms converter described does both.

The trick that makes this possible is an optically isolated rectifier input circuit (see the figure). Input voltage V_in, applied to full-wave bridge D1-D4 and LED E2, produces LED current I_e2 = (abs(V_in) − V_d)/R1 = abs(V_in)/R1 − V_d/R1, where V_d = the sum of diode and LED voltage drops. The coupled gain of the E2:P2 optical pair results in photocurrent I_p2. To balance I_p2, A1 modulates Q3’s collector current I_q3, thereby I_e1 and the E1:P1 optical pair to force I_p1 = I_p2. Due to the channel tracking that exists in a multichannel opto like the PS2501-2, when I_p2 = I_p1, we can approximate I_e2 = I_e1. LED and rectifier diode voltages will also match well, so I_e1 = I_q3 −V_d/R1. Thus, I_q3 = I_e2 + V_d/R1 = abs(V_in)/R1, making I_q3 an accurate measure of V_in that’s (almost) independent of diode voltage drops! Admittedly, this compensation only works for V_in >> V_d, but that’s good enough to maintain 1% linearity for input voltages as low as 10 V rms.

With I_q3 = abs(V_in/R1), there remains the matter of rms conversion of I_q3. This computation is based on the log relationship between V_be and collector current in Q1-Q5; the equality of this relationship among the five transistors in the LM3046 monolithic array; and the approximation that, for high beta transistors, I_c = I_e. Therefore, at any given temperature, there exist constants A and B such that V_be3 = A*log(I_q3) + B and V_be1 = V_be2 = A*log(I_q3/2) + B.

Thus, (V_be3 + V_be1) = A\[log(I_q3) + log(I_q3)/2\] + 2B. Since adding logarithms is equivalent to multiplication, (V_be3 + V_be1) = A*log(I_q3²/2) + 2B. Due to the topology of the circuit and the action of unity-gain buffer A2, (Vb3 + Vb1) = (V_be4 + V_be5). Then A*log(I_q3²/2) + 2B = A*log(I_q4*I_q5) + 2B. Cancelling A’s and B’s and taking antilogs: I_q3 2/2 = I_q4 * 1q5. Capacitor C2 makes I_q5 = the time average of I_q4 and therefore I_q4 * avg(I_q4) = I_q3²/2. Averaging both sides gives avg(I_q4*avg(I_q4)) = avg (I_q3²/2), and thus avg(I_q4)² = avg(I_q3²/2). Taking square roots of both sides yields: avg(I_q4) = root(avg(I_q3²/2)). Equivalently, I_q5 = RMS(I_q3)/sqr(2). Finally, because I_q3 = abs(V_in)/R1 and V_out = I_q5 *R3, we have at last: V_out = (R3/R1) * RMS(V_in)/sqr(2).

The prototype, with V+ = 9 V and R3/R1 scaled for a full-scale V_in of 125 V and output of 5 V, demonstrated better than 1% accuracy for V_in > 10 V and input frequencies up to 10 kHz. The circuit works accurately with supply voltages from 5 V to 15 V, but due to the way the voltage drops of D5, D6, E1, Q1, Q2, Q3, and R3 add up, V_out(max) is approximately (V+ − 4 V). So, V+ = 9 V is the minimum, consistent with a 5-V full-scale V_out. Current demand is modest at less than 2 mA.