Electronic Design
Optimal Jitter Attenuation Starts With The Proper PLL Bandwidth

Optimal Jitter Attenuation Starts With The Proper PLL Bandwidth

 

 

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Clock signals provide reference timing to every integrated circuit and electrical system. Consumer applications typically use simple quartz crystals for reference clock generation. Other applications, though, employ much more sophisticated timing requirements, often involving a combination of clocks to provide synchronization, generation, and distribution.

For example, next-generation applications for wireless infrastructure and medical imaging, which already require high-fidelity analog-to-digital signal conversion, demand higher resolution and faster data-transmission rates. Next-generation, high-performance networking and communications applications also require more speed for data transmission, plus faster data processing.

In these applications, clock signals play a vital role in the overall architecture. If designed improperly, the applications’ underlying timing solution may limit overall system-level performance. Thus, careful attention to device selection and the hardware design process helps ensure that the clocking design maximizes system performance.

The quality of a clock signal depends heavily on its phase noise and jitter. An ideal clock source would generate a pure sine wave, where all signal power is generated at one frequency.

That ideal doesn’t exist, though, because all clock signals have some degree of phase-modulated noise. This noise spreads the power of the clock signal to adjacent frequencies, resulting in noise sidebands. Therefore, phase noise, typically expressed in dBc/Hz, represents the amount of signal power at a given sideband or offset frequency from the ideal clock frequency.

Radio-frequency (RF) and analog-to-digital conversion (ADC) applications require very low phase-noise clocks. In RF applications, increased phase noise can create channel-to-channel interference, degrading RF signal quality. In ADC applications, increased phase noise may limit the data converter’s signal-to-noise ratio (SNR) and equivalent number of bits (ENOB).

While phase noise is the frequency-domain representation of clock noise, phase jitter embodies the time-domain instability of the clock signal ( typically expressed in picoseconds ). Jitter can be described as the random variation in the actual clock signal’s edges versus its ideal waveform.

Phase jitter is the figure of merit in high-speed digital applications, including data communications, networking, and high-definition video transmission. These applications require data-transmission rates as high as 100 Gbits/s. Physical-layer transceivers used in networking and HD video rely on low-jitter reference clocks that are internally multiplied within the transceiver to clock the high-speed data transmitted from the device. Excessive jitter can lead to higher bit-error rates that may exceed system-level requirements.

Managing phase noise and jitter in high-performance applications is a priority. Often, a jitter-attenuating clock IC or discrete phase-locked loop (PLL) is used to produce low-jitter clocks. A traditional PLL architecture comprises a phase frequency detector (PFD), loop filter (LF), and voltage-controlled oscillator (VCO) (Fig. 1). The PLL loop filter is usually implemented using discrete components.

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One key challenge when designing with high-performance PLLs involves choosing the “right” loop bandwidth for a given application. As with many engineering challenges, this is a tradeoff decision that must be made at the application level.

As shown in Figure 1, PLL output jitter is dominated by two sources: transferred reference noise and internal VCO noise. Reference-noise sources include jitter generated by the reference timing source, printed-circuit-board (PCB) noise coupling, and power-supply noise. VCO-noise sources include LF components, VCO amplifier components, and power-supply noise.

A jitter-attenuating PLL can be used to filter noise from the input clock and produce a low-jitter output clock. Reducing the LF bandwidth increases the amount of jitter attenuation on the reference clock, transferring less jitter from the input to the output.

If the reference clock has a significant amount of jitter, the typical remedy is to use a low PLL bandwidth to filter this noise. However, going this route may not always be advantageous. The chief reason is that VCO noise becomes the dominant PLL noise source when the PLL is configured with a very low loop bandwidth.

Unless the PLL has a very low-noise VCO, a low PLL bandwidth could actually increase  the output clock jitter. Therein lies the tradeoff decision. The PLL bandwidth needs to be set to minimize both VCO and reference jitter. Since the reference clock jitter (Fig. 2) can vary from application to application, this decision needs to be made independently on each design.

A discrete PLL built with a high-quality voltage-controlled crystal oscillator (VCXO) may be used in this situation. Still, the design is sensitive to power-supply switching noise, PCB noise coupling, and noise introduced by the discrete LF components. Another option is to use a clock IC with an internal VCO, but these devices typically require external LF components that are sensitive to external noise sources.

The interface between a PLL’s LF and its VCO is one of the most noise-sensitive nodes in a PLL design. Noise that enters a PLL through its external LF components will be present on the VCO’s input and will be multiplied by the VCO’s gain factor. This increases the VCO noise and, subsequently, the PLL noise in the design.

Solutions using discrete LFs also increase PLL design and layout complexity. PLL stability needs to be calculated for each unique frequency plan and loop bandwidth combination to ensure the design has sufficient phase margin. Some high-performance PLL designs use special PCB layout techniques, such as employing guard rings around the LF components to provide isolation and minimize leakage current. Since most traditional high-performance clock ICs require multiple isolated power planes, loop-filter layout considerations add further complexity to the PCB design.

Another approach to jitter attenuation centers around Silicon Labs’ Si5317 jitter-cleaning clock IC (Fig. 3). The Si5317 is based on the company’s third-generation DSPLL technology. It can accept a noisy reference clock at any frequency from 1 to 710 MHz, and it features two ultra-low-jitter (0.3 ps rms, 12 kHz to 20 MHz) output clocks at the same frequency. The device’s operating frequency is set using control pins, avoiding CPU intervention.

The jitter-attenuating clock includes a fully integrated, digitally controlled loop filter. Through pin control, designers can pick the optimum LF value from up to eight settings ranging from 60 Hz to 8.4 kHz. This simplifies management of the tradeoff between transferred jitter and generated jitter, which helps optimize jitter performance at the application level. Devices like the Si5317 can be added to any clock path and digitally tuned to produce the lowest possible output jitter.

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