Electronic Design
OR Gates Slash Noise Coupling In Digital Potentiometer Applications

OR Gates Slash Noise Coupling In Digital Potentiometer Applications

Digital potentiometers are extremely useful and gaining wide acceptance for controlling parameters in analog circuits. The figure shows an example circuit that uses a digital pot to change the gain of an operational amplifier. The pot in this example is controlled by a serial peripheral interface (SPI) bus, but an inter-integrated circuit (I2C) bus can also be used.

One of the potential problems of using digital pots is the chance of digital bus noise getting coupled into the analog signal path. This can occur if control-line traces run very close to the op-amp traces. Since the bus is usually very active communicating with other peripherals attached to it, noise can be continuously coupled to the sensitive analog circuitry.

The circuit presents a simple solution to this noise problem. The SCLK and SDO signals from the SPI bus to the pot run through OR gates. Consequently, the pot sees the SCLK and SDI signals only when the pot chip select line (\\[OVERBAR\\]CS) is asserted low, when an adjustment must be made.

This keeps fast-changing bus signals away from the analog circuits during normal operation. So, the potential for bus noise is limited to the time when the pot value is being changed. Therefore, noise is usually not an issue if the application requires infrequent adjustment of the pot—for example, on system initialization.

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