Electronic Design

Rate-Independent CDR Chip Locks In At Up To 2.7 Gbits/s

Using a patent-pending architecture, a monolithic, dual-channel device allows on-the-fly adjustment of data rate and eye positioning.

One of the key indicators of a fiber system's performance is how far a signal can be transmitted before it must be regenerated. A lot goes into determining this, from the quality and power of the original signal, to connectors, to noise within the fiber itself (dispersion). At the end of the day, however, everything rests on the clock-and-data-recovery (CDR) unit on the receiving end.

Given the unenviable task of having to regenerate a coherent data and clock output from what is more often than not a severely compromised signal, the CDR shoulders this responsibility in the face of multiple protocols and rapidly increasing data rates. All the while, it has to accommodate user demand for smaller footprints, lower power consumption, greater flexibility, and lower cost. This last factor, cost, acquires increasing significance as the rapid deployment of fiber-optic systems raises competition.

While CDR vendors to date have been able to answer subsets of these requirements, none has covered all the bases—until now. Using patent-pending design techniques, designers at Vitesse Semiconductor Corp. have overcome the problems. They have engineered a dual-channel, rate-agile, monolithic, CDR chip for broadband data streams that provides continuous coverage from 10-Mbit/s to OC-48+FEC (2.7-Gbit/s) rates, all in an 80-pin, thermally enhanced PQFP.

Dubbed the VSC8123, this device uses proprietary technology to provide telemetry on the condition of the incoming eye and the quality of the acquisition without taking the service channel offline. This intelligence is acquired using a microcontroller interface. The VSC8123 uses this interface to communicate with an external controller that provides the intelligence.

A key distinction is the ability to dynamically and automatically modify its acquisition point in both voltage and phase. This lets the VSC8123 acquire data in the presence of significant symmetry distortion in the data eye. Additional circuitry is provided to measure relative bit-error rates without affecting the integrity of the active data stream.

Other features include an integrated automatic-gain-control (AGC) front end with offset correction and on-die terminations, referenceless clock recovery, and customizable software control algorithms for acquisition, tracking, and error profiling.

The VSC8123 comes at a time of massive expansion in the fiber-optics arena. The Ciscos and Nortels of the world are deploying systems at unprecedented rates to accommodate the burgeoning demand for high-speed Internet access in every office, home, and soon, mobile laptops and third-generation telephones. According to Communications Industry Inc., Charlottesville, Va., the market for fiber-optic components alone will reach $6.1 billion by 2003. Also by that time, the market for dense, wavelength-division-multiplexing systems will total $6.3 billion, and the market for optical cross-connect systems will hit $1.3 billion. Heady figures, but the expansion rate certainly supports their validity.

The conversion from what was a slow, lumbering, high-end, elitist market into a dynamic, fast-moving, highly competitive field has had numerous side effects on both the business and technology. In the business, fiber-optic component manufacturers that once toiled in relative obscurity have become the darlings of Wall Street and novice investors alike. On the technology side, enormous innovation has had to take place to keep pace with increasing demand. Higher data rates have combined with multiple and varied protocols, leading to a need for higher tolerance of signal degradation, with enhanced flexibility.

Tolerance of signal degradation is crucial. As the distance a signal can go down a fiber before requiring regeneration increases, the cost of that system goes down. The time taken to deploy the system shrinks, and the reliability goes up dramatically. But some level of signal degradation is unavoidable, and its causes are numerous.

Just going down the fiber, the signal is subject to dispersive losses and jitter. This is due to the different times of flights of photons, which depend on the route they take—going down the center, or bouncing off the walls. There also are significant distortions and other losses incurred because of the electronics that are on either end of the fiber—the laser driver itself, the diode, the photodetector, and the post amplifiers that follow the photodiode. All of these tend to compromise the signal to some degree.

This degradation is measured using an eye diagram, which is essentially an oscilloscope's representation of a pseudorandom, non-return-to-zero data stream of ones and zeros. The oscilloscope triggers at a rate that isn't necessarily equal to the repetition rate of that pattern. In some cases, the pattern repeats once a second. The oscilloscope then will trigger significantly more frequently than that, perhaps 1/16th the clock rate, so a retrace is shown.

The oscilloscope is laying waveform on top of waveform. Sometimes it's a one, sometimes it's a zero. This process reduces the signal to a line across the top, which is a one. It can be either a single bit, or one two, three, or four, up to dozens of bits high before another low. On the bottom, there is some number of zero states, and then there's a series of one-zero transitions. All of that superimposed information creates the eye diagram. \[For more information, see "Taking An Eye (Diagram) Test," page 90.\] The key point is that as degradation increases, the eye starts to close, making it harder to recover the data.

Certain market trends have emerged that make this recovery more difficult. The move to noisy optical amplifiers, for instance, has made longer distances between repeater functions even more crucial. Longer spans aren't the only advantage of improved CDR ICs, however. The move to push more wavelengths (channels) onto the same fiber means that the optical launch power of each wavelength must be reduced to avoid interchannel interference. The distance, therefore, stays the same.

Improving the CDR function means that lower-quality (meaning lower-cost) components can be used. Fiber varies widely in performance from low to high grades, as do devices such as photodetectors. In fact, avalanche detectors tend to produce a significant amount of noise themselves as they detect the signal. One of the unusual characteristics about that noise is that it's asymmetrical. It tends to be noisier for the ones than it is for the zeros. A CDR device that normally would go for the geometric center would then go through fits, when in fact it may need to be biased a little lower to accommodate the fact that the error rate changes differently going up and down.

Multiple Protocols Also
All of these points are exacerbated by the overall trend toward higher data rates, combined with the need to accommodate various protocols and their respective rates. These include SONET, FibreChannel, and Gigabit Ethernet, to name just a few.

While 2.5 Gbits/s was the peak rate a couple of years ago, it is now merely a starting point for many systems, with a growth path to 10 Gbits/s already being ironed out. Even so, the CDR circuit must still be able to handle the myriad of lower rates.

Traditionally, this was accomplished using banks of CDR ICs and lots of switching between them. But distributors of fiber-optic equipment have become more demanding, and rightly so. The banks of CDR devices take up too much room and consume too much power, leading to a push for one-type-fits-all devices with multirate capability.

Micrel Semiconductor, San Jose, Calif., a provider of high-performance, mixed-signal solutions, has led the way in that aspect with its SY87701V and SY87700V protocol-independent devices. These devices range in frequency from 32 Mbits/s to 1.25 Gbits/s, and 32 to 175 Mbits/s, respectively. The selection is made manually through a jumper and the reference-clock selection. Other companies, such as Lucent, perform the selection in the fab, leaving little or no room to maneuver. The ultimate goal, of course, is to be able to monitor the input frequency and have the CDR device adapt accordingly on the fly. That's partly what Vitesse's VSC8123 is all about, along with the ability to precisely optimize where in the eye the sample point is taken, with respect to both voltage and phase.

According to Gary McCormack, the lead architect of the device, it was built to overcome "a lot of tweaking and tuning that was wrapped around a CDR chip to optimize its acquisition of the data." It's common in systems to have a digital-to-analog converter (DAC) that provides a small offset at the input of the CDR. They also may use things such as overhead/performance monitors to examine the error rate—typically done in software. Other chips have an adjustable phase-acquisition capability where they slew the tap around so that a flip-flop (FF) actually samples in the eye. These fairly crude functions don't offer a lot of steps of resolution in their ability to adjust. Also, they're built into some ICs, meaning they're not easy to add after the fact.

Additionally, some designers might mess with the PLL operation to try and modify the sample point. But again, McCormack says, it's kind of crude to do that. The VSC8123 took a completely new approach, from the ground up (Fig. 1).

The initial stage, frequency recovery, is fairly conventional. It's essentially a data-driven clock-recovery loop, similar to most any CDR and fed by an AGC front end with a 40-dB dynamic range. External control is provided for loop gain and offset compensation, allowing the AGC function to be monitored and modified if need be. A line-level input is included, permitting the AGC function to be bypassed and replaced with an external gain block.

The one thing about the clock-recovery loop that made it a little bit easier to develop is that it doesn't have to worry about what phase clock it produces. All the loop cares about is the frequency of the incoming data. Its sole purpose in life is to extract clock frequency. It uses an analog control loop that locks to the incoming data rate without requiring an external clock reference. A portion of the loop filter is taken off-chip so the loop bandwidth can be externally modified.

Variable Clock Produced
The recovery loop produces a multi-phased clock output, which is then used to create a variable-phase version of that recovered clock. The clock is essentially split up 64 ways to produce a variable-phase clock of 0° to 360°. That clock is then used to strobe an FF, which is looking at the incoming data stream. Adjusting the phase moves the sampling point of that FF across the entire span of the incoming data eye.

The designers spent a lot of time on the front-end amplifier and fine-tuning the FF to achieve the narrowest capture window possible. The setup-and-hold time of the FF is a key parameter in how much eye closure the system can tolerate. Unfortunately, it can be difficult to obtain an accurate measurement of the setup-and-hold time because the behavior of FFs becomes very statistical as the limits of their operating range are approached. That's significant.

According to McCormack, "We're recognizing that the whole nature of the capture of information is a statistical problem, in the sense that even when the device appears to be clocking cleanly, there can still be errors introduced, and these tend to be of a statistical nature." Although there's still some disagreement over the cause of these errors, or whether or not they truly are statistical (as opposed to deterministic), McCormack and crew got around the problem by allowing the sampling point to be moved to a point in the data eye where the probability of error is lowest.

In front of the latch is a fully differential, variable, slicing-threshold comparator that permits adjustment of the slicing level of the incoming data stream in voltage. At this point, the chip lets the user vary the sampling point in both voltage and phase. This is close to how existing systems are done discretely. For example, some companies will take a simple CDR chip and wrap DACs and other blocks around it to make these same adjustments. The designers at Vitesse then created a patent-pending circuit architecture to implement a monolithic version of that.

The next step was to incorporate into the chip itself the ability to monitor and judge its own sampling performance without requiring information from a higher-level element in the system, like a performance monitor downstream. This was accomplished using a secondary channel. Now the chip has frequency recovery, with two variable-phase outputs, or two acquisition channels, each independently adjustable. Each looks at the same data stream, but they can be adjusted to sample the data stream at a specific voltage and phase for each of the channels. The output of both of these can be used to deduce quite a bit about the voltage/ phase decision's ramifications.

For instance, one of the channels can be placed in the center of the eye where it's gathering clean data, and the other channel can be used to scan in both voltage and phase (Fig. 2). At the exact same point, they'll agree with each other. But as one channel starts to move away, it'll reach a region in the data eye where it'll start to get a result from the data stream that disagrees with the center channel. That sort of scanning can be used to deduce where the center of the eye is by placing one channel near the center and sending the other for a walk to essentially feel out the interior of the eye diagram to approximate the center.

From here, it's up to the user to determine which algorithm to use to determine the center. In other words, it's a software problem like the Q test, where the algorithm will look at the slope of the error rate and extrapolate to the center. There also are ping-pong and center-of-gravity algorithms, each having its relative benefits depending on the system's requirements.

Part of the idea is to provide a sufficiently open-ended architecture so end users can write their own proprietary algorithms into the part and somehow differentiate their applications of the part from someone else's. Usually the customer is stuck with whatever the vendor has chosen for determining the center of the eye.

The second channel allows other unique features. Assuming the first channel is centered, the secondary channel can conduct some online performance monitoring without affecting the data stream, which stays active. Using the simple, built-in, 10-bit microcontroller interface, information about the eye—such as the quality of the acquisition, as well as test functions and profiling—can be gleaned without sending out a technician. The designers also included what they call "rate agility" with the part, so it runs in any frequency from 10 Mbits/s up to OC-48+FEC (2.7 Gbits/s). That's not an easy feat.

One of the issues that comes into play when running a broadband recovery unit is false locking, where the device locks on to some sub- or super-multiple of the data rate. This isn't an issue in single-rate CDRs, where the oscillator's range is limited. In multirate systems, though, a wider oscillator range makes it more likely for the system to pick up some super-/sub-harmonic—most notably things like 3/2s and 2/3s.

The VSC8123 uses the dual-channel architecture to perform some measurements on the eye. These measurements are used to audit the acquisition to determine whether or not it's locked to some multiples. The external controller operating the chip then determines whether or not it has false-locked. This external controller is usually on the board anyway. If it isn't, it can be implemented using FPGAs or any third-party device. The designers chose Microchip's PIC14000 because of its low cost and low power consumption.

The dual-channel feature has other uses, as well. It enables the device to deal with a lot of manufacturers' variations and tolerances by essentially ping-ponging the two channels between each other. As one channel goes for a walk and determines its optimum position relative to the other channel, the chip is able to seamlessly autoswitch between those two acquisition channels. There's no interruption in data. The ping-ponging avoids the problem of calibrating the two channels with respect to each other. This tolerance takes a lot of pressure off the accompanying technology. The second channel also can serve as an alarm, alerting the host to deviations in the eye envelope beyond predetermined limits.

While the VSC8123 represents the cutting edge of CDR technology, Vitesse's competition is well aware of the advantages of continuous-rate (or in Micrel's terms, "Anyrate") recovery, and will not be long in following suit. Customers are demanding it. As a result, more announcements in this realm can be expected over the coming months.

The VSC8123 operates off 3.3 V, consumes 2.1 W, and has an operating temperature range of −40°C to 85°C.

Price & Availability
The VSC8123, sampling now, is priced at $160 each in lots of 1000 units. Vitesse is working on firmware and programming algorithms.

Vitesse Semiconductor Corp., 741 Calle Plano, Camarillo, CA 93012; Greg Borodaty, (805) 388-7435; fax (805) 987-5896; [email protected] com; www.vitesse.com.

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