Hardware designers are feeling the pressure from designs with continually accelerating memory or SERDES protocol links, while facing shrinking margins and unrelenting cost constraints. I believe we have finally reached the point where “sign off” verification is a requirement on these interfaces before going to your first layout.
What is signoff verification? Reviewing your board to see if you match the IC vendor’s product-development guide? Simulating every high-speed net on the board with IBIS models? What about power integrity? IR drop? Decoupling analysis?
As a tool provider, I would say signoff verification encompasses all of the above… but to what extent? You could try and do everything with full 3D extraction, adding detailed package models… does your watch have a third hand for days of the week? Maybe you have had success just doing manual inspection of the layout based on the platform IC vendor’s guidelines (e.g., length matching, impedance, and decoupling requirements).
At Mentor, we sponsor the annual Technology Leadership Awards and get hundreds of boards submitted from around the world, so we get a pretty darn good idea of what’s going on out there. Have you seen how dense some of these boards are becoming? Manual inspection is crazy difficult—error-prone at best.
What’s Your Comfort Level?
How do you triage the board and find out what nets need your attention? Maybe the first question should be, what type of verification are you even comfortable with? Are you a hardware designer? Okay, then you’re comfortable with waveforms, setup-and-hold times, and differential impedance. But maybe you’re not a DDR4 protocol expert and are unfamiliar with write leveling or slew-rate derating tables. Or maybe you understand those, but aren’t comfortable with defining ports to a 3D EM solver. My guess for you: rules and waveforms are both okay.