Fig 1. Good signal integrity is verified by a clean eye pattern with the bit pattern forming an “open” eye around the HDMI eye mask. In this eye-mask screen capture, the first pattern (a) is used as a reference, illustrating the HDMI video signal without any protection devices in the circuit. The second pattern (b) shows virtually no impact after the addition of the integrated TVS protection device. In this test, the TVS device is a Semtech RClamp0584J, which is also applicable to DisplayPort, ExpressCard, eSATA, and other high-speed interfaces.
Fig 2. The RClamp2574N used in the Gigabit Ethernet example has a typical capacitance of 1.7 pF line to line, which is low enough to avoid any packet loss or packet errors.
Fig 3. Following the recommended circuit board layout for specific devices, the Rclamp257N described in the example is an important part of ensuring successful protection.
Supported by ubiquitous broadband access, the smart television has all but replaced the traditional TV. With a smart TV, high-definition digital content can be streamed and customized from the “cloud” onto any device connected to the Internet, or it can be written to a physical disk and played back on demand.
Smart TVs are television sets with integrated Internet capabilities that offer advanced computing ability and connectivity. To achieve versatility, a smart TV usually utilizes the latest generation of technology, including smaller, more functionally complex ICs.
That decrease in feature size and increase in circuit density leads to new challenges in electrostatic discharge (ESD) and cable-discharge events (CDEs). However, designers can use transient voltage suppression (TVS) ICs to develop protection schemes for the two most common and sensitive interfaces on smart TVs—the High Definition Multimedia Interface (HDMI) and Gigabit Ethernet.
HDMI ESD/CDE Protection
HDMI has gained in popularity since its inception. It is widely adopted across the consumer electronics industry to transfer high-definition digital content. But as a high-performance interface, HDMI can be extremely vulnerable to cable discharge from a hot-plug cable and ESD directly from the user.
To ensure proper functionality, HDMI-based systems must protect all potentially exposed interface signals and power pins to meet or exceed the electrical over-stress (EOS) specification of IEC 61000-4-2, Level 4 (±15 kV Air, ±8 kV Contact) without damage. Current HDMI silicon runs at 2.25 Gbits/s with 3.4 Gbits/s in the near future.
At such a high data rate, signal integrity and impedance requirements are given more focus than ever before, as put forth in the HDMI Compliance Test Specification (CTS). The HDMI CTS requires all HDMI sink devices to maintain the differential impedance of the high-speed lines at 100 Ω ±15%.
At a data rate of 3.4 Gbits/s, providing low-clamping voltage protection without adding excessive capacity loading is critical. To effectively arrest transient surge to low clamping voltage, more silicon area in the TVS diode is required. Increasing silicon die area comes with the cost of higher capacitance, though.
This tradeoff dynamic can be overcome by building a low-capacitance diode array around a surge-handling TVS diode, effectively lowering the total capacitance of the protection circuit while preserving robust surge protection. The RClamp0584J is an example of such an integrated TVS protection device. This four-line, 5-V working voltage protector is rated in excess of IEC 6100-4-2 level 4 to guard against electrostatic transients.
Adding ESD protection to the HDMI interface should not significantly impact signal integrity. Eye pattern testing does not reveal signal distortion on the source interface. (Fig. 1).
Gigabit Ethernet Surge Protection
A major feature that distinguishes a typical smart TV from a traditional one is Internet connectivity, which is achieved by an Ethernet connection. Gigabit Ethernet has been widely adopted on new smart TVs. It operates at 125 MHz and transmits and receives (full duplex) on four twisted pairs. It also uses a bi-directional five-level coding scheme that requires a complex physical-layer (PHY) chipset.
The latest Ethernet PHY chipsets are typically manufactured on 65- or 45-nm technologies. These small geometries yield higher levels of performance, but also result in an increased level of sensitive to fatal damage that may originate from a charged cable, lightning, or a “human body.”
Traditionally, ESD and CDEs have been considered the typical transient threats for Ethernet interfaces on computers or consumer electronics. Lightning or surge protection is mostly reserved for communications infrastructures. In recent years, computers and consumer electronics have become more affordable thanks to technological advances.
While more people from all over the world are able to have their own computers and/or TVs, these very electronics are brought into some of the more hostile environments as far as transient threats are concerned. China, for example, has just mandated an Ethernet surge protection requirement for electronic products sold into certain rural parts of China. This new standard ensures a reasonable functional period of expensive products and the safety of the households operating them.
The Chinese surge tests are applied as metallic (line-to-line) or longitudinal (line-to-ground) waveforms. The waveforms are defined with a rise time of 10 μs and a decay time of 700 μs with an open circuit voltage of a customer-defined level no less than 1 kV. Positive and negative polarity surges are applied. To pass, the equipment must continue to operate after the tests.
An Ethernet port includes transformers and common-mode chokes for connecting the PHY to the outside world. Transformers and chokes can be discrete components, but integrated solutions that include the RJ-45 connector, resistors, and capacitors are becoming increasingly popular. In either case, the transformer will provide a high level of common-mode isolation to external voltages, but no protection for metallic surges.
For a metallic (line-to-line) surge, current will flow into one line, through the transformer, and back to the source. As the current flows, it charges the windings of the transformer on the line side (RJ45 side). Once the surge is removed, the windings on the line side will stop charging and will transfer its stored energy to the IC side where the PHY IC is located. The pulse transferred to the PHY side will most certainly be destructive to the PHY chip.
Reliable protection of the Ethernet transceiver requires an external protection device that can absorb the expected transient energy, clamp the incoming surge to a safe level quickly, and yet remain transparent to the system under normal operation. The capacitive loading and package must be optimized to minimize the impact on the differential pair signal integrity. Additionally, each new generation of Ethernet deployment yields higher-density boards that demand protection solutions that occupy less board space.
Other Suppression Devices
TVS ICs aren’t the only kinds of suppression devices. There are also polymer devices that use tiny metal particles suspended in a polymer matrix and discrete diode solutions. Decisions about what to use should be based on the application. The ideal protection device should remain invisible during normal operation, turn on immediately in an event of an ESD strike, and limit the voltage across the protected devices to a level just above the normal operating voltage and well below the destructive threshold.
Polymer devices are attractive for protecting high-speed interfaces because of their small size, ultra-low capacitance, and low leakage current. These characteristics are desirable to minimize board size while maintaining signal integrity and battery life. However, polymers fail on one of the most important characteristics for system protection—clamping voltage.
By definition, clamping voltage is the maximum voltage drop across the protection device during an ESD event, which is also the stress voltage seen by the protected IC. Polymers typically have an initial clamping voltage above 1 kV, which will very likely damage today’s sensitive ICs. Furthermore, polymers degrade after repeated surges, which results in leakage current increases.
Back-to-back BAV99 rectifying diodes in SOT-23 packaging are sometimes chosen to offer protection in a rail-to-rail configuration, but they offer a small junction area. Also, their limited transient current ratings are below what may be expected in ESD and lightning events.
In a typical configuration, the BAV99 diode pair would connect the power rail/signal line and ground so that during a positive surge, the top diode would turn on and conduct the high current to the power rail/signal line, which is not advisable. In contrast, a pair of surge-rated steering diodes can be integrated with a TVS diode in the same package. The TVS creates a path to dump the high current to ground instead of through the power rails.
Design Example
Let’s look at an example based on the RClamp2574N, a Gigabit Ethernet protection solution from Semtech (Fig. 2). In practice, it should be placed on the PHY side of the transformer as close to the magnetics as possible. The device can be configured to protect all four differential pairs on a Gigabit Ethernet.
Each of the eight I/O pins features a low-capacitance steering diode pair designed to route harmful surge current into the internal low-voltage TVS diode. The steering diodes have a working voltage of only 2.5 V and are constructed using Semtech’s proprietary EPD process technology \\[1\\].
Low-voltage turn-on is important since many PHY chips have integrated ESD protection structures. These structures aren’t designed to handle large amounts of energy. Should they turn on before the external protection, they can be damaged, resulting in the failure of the PHY chip.
The working voltage of a typical Gigabit Ethernet PHY is 2.5 V. Therefore, a 2.5-V TVS should be chosen because a 2.5-V TVS will turn on immediately once the hazardous voltage across it has exceeded the punch-through voltage of the device.
Routing the printed-circuit board (PCB) trances through the device is important (Fig. 3). Data lines are connected at pins 1, 2, 4, 5, 6, 7, 9, and 10. Pins 3 and 8 are electrically connected to the three center ground tabs. In a typical Ethernet application, these pins as well as the tabs should be left floating (i.e., not connected to ground).
In this example, traces are 0.005 in. wide. Vias are used to change layers for connection to pins 6, 7, 9, and 10 and, hence, enable an easy flow though layout for all eight data lines.
Smart TV employs the latest technologies and in turn presents unique protection challenges. Good transient suppression requires state-of-the-art protection schemes that reduce the transient surges to a safe level while maintaining system signal integrity.
By choosing proper protection solutions early on, designers can eliminate the unnecessary time spent on redesigning layout when transient threats become a problem later in the design cycle and therefore expedite the time-to-market in the competitive consumer electronics industry.