Electronic Design

"Sample Wars" And Silicon Technologies Energize ADCs

To "win the socket," some chip vendors turn to virtual silicon samples and new process technologies. Others rely on creative design.

Some big chipmakers have been looking to maintain an edge in the frenetic pace of the electronics industry partly by upgrading their online development tools beyond simple parametric device selectors. This has led to the creation of more comprehensive tools that link all design parts. In addition to these tool upgrades, they have begun moving from their own custom tool toward standardizing on National Instruments' LabVIEW as a common interface and engine.

National Semiconductor's Webench tool, for example, helps circuit designers select an analog-to-digital converter (ADC) and create any kind of anti-aliasing filter desired for the input signal path. It also assists them in creating the power supply needed to run the whole circuit.

Analog Devices' director of applications engineering, Dave Kress, provided the most cogent explanation of why companies are turning to these online tools. "Chip vendors vie with each other to get samples and eval boards to customers, because often, the first to get a chip into the engineer's hands wins the socket," he says. "These tools are a way to beat the 'sample wars' game." According to Kress, the tools also provide a way for field application engineers to kick-start customer engineers, who can then safely be left to their own devices (double entendre intended).

A HANDS-ON DEMO
I got to test-drive ADI's signal-path design tool with applications engineer Travis Harkness to see what the experience was like (Fig. 1). I used the tool's setup wizard to create a case in which we intended to use an op amp in non-inverting mode to condition a bipolar signal from a sensor and scale it to a 0- to 2.5-V input to an ADC.

When I clicked "Find Amplifiers," I got a long list of potential ADI parts. Some had notes, cautions, or alerts adjacent to the part number. A "Note" points out something the design engineer could do to make the circuit work better. A "Caution" indicates something sub-optimal that might dictate a circuit change. An "Alert" indicates that while the part meets the basic selection criteria, there are reasons it shouldn't be used.

From the list, Harkness first had me select the AD711 marked "Note" in the selection table and return to the evaluation tool. At this point, the circuit diagram showed the reference voltage and component values required.

After I hit the "run model" button, a graphic representation of input and output waveforms appeared. Also, under "log," a message said "Note: Typical Gain Error Exceeds 1%. Due to the amplifier's frequency dependent open loop gain, along with the selected closed loop gain and frequency, the calculated typical output error exceeds 1%. Possible solutions: Lower signal frequency or reduce closed loop gain."

Harkness noted that he had me select this amplifier precisely because it didn't have enough open-loop gain at higher frequencies to meet the design's required gain. Unlike SPICE and other simulators, in which you could see a problem but not necessarily understand where it came from, ADI wanted the tool to explain the underlying reasons why a part might prove unsatisfactory.

Gain error had a small effect at the first input frequency we chose—100 kHz. So Harkness had me increase the frequency to 3 MHz in the box in the GUI and rerun the simulation. This time, distortion was visible in the output waveform, and the "log" box message now read "Caution: Amplifier slew rate exceeded. Signal distortion and excessive errors may occur. Possible solutions: Reduce signal frequency, lower signal amplitude or reduce closed loop gain."

This illustrated the tool's value well, because the amount of distortion was still subtle. Harkness said it might not have been visually detectable in the waveform if we'd used 2.4 instead of 3 MHz, and using Spice, we may not have even noticed it.

While its ability to point out what won't work is useful, the tool's real benefit is in accelerating the search for the right answer. Next to the amplifier wizard box, there's a "suggest amplifier" option. Hitting that button sent me to a screen where I re-entered key parameters. Hitting "find amplifiers" returned a smaller set of acceptable part numbers (smaller because the input frequency remained at 3 MHz), which I could further evaluate.

THE WEBENCH SIGNAL PATH TOOL
National Semiconductor's Webench Signal Path Designer (signalpath.national.com) works somewhat differently, but it's equally user-friendly. A voice-over demo on the Web page provides a walk-through. The user can select an ADC first or design the response of the anti-aliasing filter. The demo takes the latter path.

The user first defines some ADC characteristics, operating voltage, number of channels, resolution, sample rate, maximum frequency, and operating temperature range. This produces a list of NSC's ADCs that satisfy those criteria, and the best-fit converter is selected.

The next step is to define the anti-aliasing filter's primary characteristics: input voltage, maximum permissible deviation within the passband, and attenuation at the ADC's Nyquist frequency. Once defined, an array of filter types is presented—Bessel, Butterworth, and a number of Chebyshev variants. Designers can select as many as they want, though the more they select, the longer it takes to produce a set of results.

These results consist of graphic presentations of the filters' response characteristics: frequency and phase response, group delay, and step response (Fig. 2). Here, the demo selects the Bessel filter design, for the sake of the relative lack of ripple in its step-input response.

Given the desired filter characteristics and type, Webench Signal Path Designer offers a selection of National op amps that can implement the filter. All characteristics, including price, are listed. Once the user selects one, Webench creates the design, listing all components and tabulating all the design's behaviors.

Currently, the Webench Signal Path tool handles conversion rates from 50 ksamples/s to 1 Msample/s. Its database contains 85 8-, 10-, and 12-bit data converters and 220 amplifiers. The tool's active filter designer handles third-order filters.

By January, Webench will be able to deal with speeds of up to 100 Msamples/s, Fourier transforms, and filters up to ninth-order, as well as provide design advice. By June of 2006, it will handle conversion speeds reaching 1.5 Gsamples/s, import and export netlists and other CAD data, and offer a database of roughly 150 converters.

UNDER THE HOOD
Chip vendors started out creating their own point tools for product selection. More frequently, though, they're turning to National Instruments' LabVIEW, which was originally developed as a test instrument controller and datamassager as the front end for their simulations.

"We conducted a survey with Tektronix earlier this year. Roughly 25% of the respondents said that parts selection and evaluation formed the biggest bottleneck in the design process," says Richard McDonnell, National Instruments' test-stand and switch executive product manager. At the same time, he adds, "chip vendors are now sensitive to the challenges that engineers found in using the vendor-specific tools they provided in years past."

Both chip and instrument vendors, he says, have had customer feedback indicating that if they could leverage some of the industry-standard tools out there, such as National Instruments' LabVIEW, designers would feel more comfortable with the tools. There would be an immediate sense of familiarity because of the common modes of input and the consistent way that results are presented. Then when the engineers are ready to request a couple of actual evaluation boards, they can, within the same measurement environment, compare results captured from real signal sources and measured with real instruments with the simulation.

"Once the design engineers have narrowed down their search to a reasonable number of parts, that's when they really want to start digging and beating on the part to understand the limitations the data sheet doesn't disclose," McDonell says. "Surveys tell us that's what can take several weeks per part to uncover. So the ability to transition easily from the virtual chip to eval board is critical."

Not everyone has gone through the same customer experience. Robert Reay, VP and GM of Linear Technology's mixed-signal business unit, explains that while Linear is in touch with NI, it's continuing to use its own custom tools, written in C. "At the moment, customers are not telling us they want models," he says. "They still insist on real samples."

NI's latest collaboration with ADI is a software product called Signal Express. It operates on top of Lab-VIEW to provide a more interactive, drag-and-drop, non-programming measurement experience. Designers use drag-and-drop to specify any kind of arbitrary input waveform they want and then post-process the data coming out of the model—fast Fourier transforms, filtering, whatever they want.

NEW MIXED-SIGNAL PROCESS TECHNOLOGIES
Recently, NSC and ADI announced new process technologies for the datapath that conditions and feeds analog signals to ADCs and/or for mixed-signal products. Over the summer, NSC disclosed its VIP50C technology, a silicon-on-insulator CMOS process optimized for amplifier applications. It will allow amplifier products to be created in a 0.9- to 12-V supply voltage range, covering everything from ±5-V split supplies to lithium-ion and nickelcadmium battery-driven applications. The bipolar components are high-speed vertical npn and pnp transistors.

VIP50C uses trench isolation in a silicon-on-insulator (SOI) technology, which minimizes parasitic capacitances. Trench isolation on SOI also provides the ability to process signal voltages exceeding the positive supply voltage as well as negative input voltages. Furthermore, the effects of leakage currents that limit performance at extremely high temperatures can be eliminated, opening up industrial and automotive applications.

Analog Devices announced a highvoltage mixed-signal process technology for industrial applications called iCMOS late last year. Using bulk silicon rather than SOI, it relies on junction isolation underneath high-voltage devices and on deep wells for low-voltage devices.

With iCMOS, ADI can integrate small-geometry digital logic with highvoltage, fully complementary bipolar devices. Chip users can apply as much as 30 V across a chip with submicron geometry. New iCMOS products comprise 12- to 16-bit ADCs with softwareselectable inputs, allowing for wide input ranges from ±2.5 to ±10 V while providing 85% lower power consumption than previous chips.

This past June, ADI announced its iPolar process technology for signalpath chips. For iPolar, ADI again rejected SOI, this time in favor of a proprietary deep-trench-on-bulk-silicon isolation scheme for maintaining junction isolation between the devices and the substrate. The idea was to keep costs low and provide good thermal conductivity for the active transistors.

EXISTING TECH FLOURISHING
Several companies are pressing forward with process-technology advances that promise plenty of life for current-generation geometries. For instance, Linear Technology and Texas Instruments have released advanced delta-sigma products in those company's CMOS silicon technologies (see Analog & Power TechView, p. 26).

One radical new ADC, fabricated in mainstream CMOS and developed by a previously little-known fabless company from Germany, shows what can result from creative intellectual property. The new delta-sigma product, on 130-nm silicon, offers exceptionally low power per conversion and handles input-signal amplitudes greater than the chips' operating voltage.

That German company—Xignal— previously offered SERDES IP products. In Xignal's case, such expertise made possible a breakthrough in bringing continuous-time delta-sigma to the wider market (see "Continuous-Time Delta-Sigma Converters," Drill Deeper 11289, at www.elecdesign.com).

Its advantages include ultra-low power per conversion, elimination of anti-aliasing filters, the presence of a high-performance LC-based resonator and phase-locked loop (PLL) on-chip, and a technology that's not limited by CMOS scaling issues. Applications cited for this initial product are ultrasound, automotive collision-avoidance systems, and communications test and measurement equipment.

Xignal announced that sampling parts are scheduled for later this year, but prototypes are working in the lab (Fig. 3). The initial product employs a third-order, continuous-time delta-sigma modulator with a 4-bit quantizer stage that oversamples by a factor of 16. The internal sample clock operates at 640 MHz. Its self-adaptive, tunable loop filter supports sample rates from 20 to 40 Msamples/s. The fully differential input-signal path features a 30-MHz bandwidth.

The data stream from the modulator is fed to a cascaded multistage digital filter, designed to optimize phase and amplitude performance at the lowest possible power dissipation. Future family members will offer resolutions ranging from 12 to 18 bits and sample rates in hundreds of megahertz. Up to 80-Msample/s rates (at 14 bits) are anticipated, with an oversampling clock rate of approximately 1.3 GHz.

A key ingredient in Xignal's ADC is a high-performance clock source integrated on-chip with the core. The only external component needed is a low-cost crystal, parallel-connected to the clock input. The clock is connected to a high-performance PLL block that uses an on-chip, LC-tuned circuit to create a high-Q resonator, creating a very precise clock source.

It's also possible to use an external clock to drive the ADC. In that case, any high-frequency jitter from the external clock tree will be removed, provided its jitter falls outside the 350-kHz PLL bandwidth of the jitter cleaner circuit. A better idea, however, might be to route the on-chip precision clock to external circuits, using it as the system reference clock.

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